Combinational Logic w/o Component

In both Verilog and VHDL, it's NOT always necessary to build smaller components and then use the correct port mapping to form a larger circuit. Sometimes it's more efficient just to build it programmatically.

But when is a good time to use smaller components? When is a good time to just build the whole circuit?

It is up to the designer, but I will give one example of each.

Let's say you were building a Computer. This is a very complex scenario where you might want to build it out of smaller components. You can build the RAM, CPU, etc as separate components and put them together. In CPU is still very complex and can be broken down to smaller components. In this method, we can test individual components using test bench files and then just wire them up properly using a port map to connect all the pieces. If there are problems we know, there is a higher possibility that the problem is with the wiring up since your smaller modules have been rigorously tested. The only time that there might be a problem with a module is if it goes into a state that hasn't been tested.

Below is a circuit design using AND, OR, and NOT Gates. Instead of building the circuit in Verilog/VHDL by connecting up AND, OR, and NOT Gates with port maps, we can simply use logical programming.

Verilog - Combinational Logic using logical operators

VHDL - Combinational Logic using logical operators