Deploying More Verilog

Objective

• To gain more experience with an FPGA

• To gain more experience with Verilog

Prelab

Complete The Verilog portions of HW 9

Deploy your designs to an FPGA

Build the following circuits and test them on an FPGA

• 4:1 mux

• 1:4 demux

• positive edge triggered DFF

• positive edge triggered JKFF

• 4 bit BCD up/down counter

• A generic ALU (specifications are given in HW 9)

The display is made up of 7 LEDs, each controlled by distinct inputs labeled a, b, c, d, e, f, and g. If a pin is asserted then the LED will light up. By asserting the right combination of pins, the display can show characters. 

For example, here is a list of characters (including the space character ' ') and their corresponding combination of inputs: 

     Character     a     b     c     d     e     f     g

        'A'        1     1     1     0     1     1     1

        'L'        0     0     0     1     1     1     0

        'O'        1     1     1     1     1     1     0

        'H'        0     1     1     0     1     1     1

        'P'        1     1     0     0     1     1     1

        'U'        0     1     1     1     1     1     0

        ' '        0     0     0     0     0     0     0

The inputs to the 7-segment display are in negative logic. 

The scrolling door sign should work as follows. If the switch is turned on then the display should scroll through 

'A', 'L', 'O', 'H', 'A', '  ', '  ', 'A', 'L', 'O', 'H', 'A', '   ', '   ', .....

which indicates that the professor is in. Note that there are exactly two spaces between ALOHAs. 

On the other hand, if the switch is turned off then the display should scroll through 

'P', 'A', 'U', '  ', '  ', 'P', 'A', 'U', '  ', '  ',.....

which indicates that the professor has gone home. Note that there are exactly two spaces between PAUs. 

Your circuit will have : 

• A clock input. This will be connected to a clock generator (preferably your oscillator circuit from Lab 3, and you may adjust the clock period so that the scrolling goes at a proper rate (say a clock period of around half a second). 

• An input DI. This is connected to one of your Logic Switchs. So if DI = 1 then the Doctor is In and the ALOHAs should scroll on the sign. On the other hand, if DI = 0 then the doctor is out, and the PAUs should scroll. DI will be in positive logic. 

• Outputs that go to the 7-segment display. 

Task 1: Design & Simulate

• Complete a neatly drawn state diagram for the circuit.

• Complete a neatly drawn ASM chart for the circuit. 

• Note that your output boxes may have a large list of outputs for the 7-segment display, making it difficult to draw. You may use the following informal shorthand notation: 

• Convert your State Diagram or ASM chart into a State table. 

  • Note: you will need at least 7 states in your FSM, thus requiring 3 state bits to encode the state. With 3 bits of Next State values, and 7 outputs for the 7-segment display, this is 10 outputs from the combinational logic.  

  • Simplification is possible and there may be a way to simplify your design by eliminating outputs or implement some outputs using simple external logic. 

• Complete a working Circuit Diagram in the simulator using a ROM.

  • The Circuit Design using AND, OR, and NOT gates may be very large. You can implement a ROM for output logic. You could also use a ROM for Next state logic as well.

Task 2: Verilog

• Implement your designs in Verilog using the 3 block method.

• Write Test Benches to test your Designs

• NOTE: you could test your VHDL skills if you wanted here but the 3 block method is the same with different syntax.

Task 3: Deploy onto an FPGA.

In Task 2, you have created the source HDL file in Verilog. In this task, you should deploy your circuit onto an FPGA.

• Deploy your verilog code onto an FPGA BASYS3 using Xilinx Vivado

  • Supply source files

- HDL model, in this case we can use any of the Verilog files above.

- User constraint file

• • Run a behavioral simulation to verify model functionality

- Behavioral simulation will produce waveforms to be analyzed.

• • Synthesize Model

- Synthesized model produces a logic diagram of our HDL model.

• • Implement Model

- The implementation process shows us the hardware implementation of our logic on the specified board.

• • Generate a bitstream.

  • Run a timing simulation on implemented design.

  • Verify functionality in hardware by connecting board and uploading bitstream.