Become familiar with Verilog HDL and VHDL
Use Verilog and VHDL to program simple gates
Make sure to review the Material on the Intro to Verilog & VHDL page.
Read through the lab material before your lab session.
Test the provided Code for AND, OR, and NOT gates in Verilog using the correct test bench.
Verify that you understand at least these basic gates in Verilog and VHDL
Build NAND & NOR Gates in both Verilog
Build XOR and XNOR Gates in both Verilog
These are both HW Questions. You can use the extra Lab Time to learn this.
Use the Lecture notes to build a simple ROM in Verilog
Build a 2bit x 2bit multiplier ROM
Implement a Full Adder in Verilog by using any method you learned so far.
Implement an 8-bit ripple adder in Verilog by using the full adder you created earlier. (Use 8 Full Adders and Port Map Correctly)
Build a test bench to test your 8-bit ripple adder
Implement a 4-bit BCD to 7 Segment display using Verilog
Unlike Task 4, you should NOT build this using AND, OR, and NOT gates. Instead, you should use logical Operators.
For Task 1 - Task 5. Load you code onto the FPGA used in the class.
Become Familiar with Vivado
Demonstrate the functionality of the FPGA to your TA.
Include this discussion in your lab report.
Tell me how you can use your module from task 5, and the techniques from task 4 to create a BCD to decimal display that displays any number fro 0 to 1023.
The original numbers are in binary. How many bits do you need to represent all numbers
The output should be multiple 7 segment displays. How many 7 segment displays do you need
Make a quick drawing showing how to connect everything up.