You should become familiar with the two books in this course for Verilog and VHDL. The table of contents will help a lot. We will use these textbooks as a reference when building Verilog or VHDL. You can find the textbooks (Quickstart Guides) in the Syllabus under the Textbook Sections.
Read the following sections.
Verilog
Read Chapter 1 (8 pages with lots of pictures)
Browse Chapter 2 - this chapter has useful information for setting your code up
Variables, Modules, Port Definitions, etc.
Read Section 3.1 (6 pages)
VHDL
Read Chapter 1( Not needed since this is the same as the Verilog Book)
Browse Chapter 2 - this chapter has useful information for setting your code up
Variables, Modules, Port Definitions, etc.
Read Section 3.1 (4 pages)
You can find working Examples using the EDA Playground Links Below
Verilog Settings
Testbench + Design - SystemVerilog/Verilog
Tools & Simulators - Icarus Verilog 0.9.7
VDHL Settings
Testbench + Design - VHDL
Top entity - Set to the name of your top entity in your test bench
Tools & Simulators - select GHDL 0.37
NOTE: In the EDA Playground the file extensions are: .sv (veriolog) and .vhd(VHDL)
Usually, I use a different system to grade (Linux). So when you turn in any files make sure your verilog files have a .v extension and your VHDL files have a .vhd extension.
DO NOT USE .sv (Thanks for Reading this)
Raw Text files Download Link: Verilog&VHDL.zip