Transistors, NMOS, PMOS, CMOS Logic

Transistor

You will be learning about transistors in depth a little later as Electrical Engineers. Right now, I'll give some of the basics in order to give you a more solid background on how these logic devices work.

There are two basic types of transistors. There is the BJT (bi-polar junction transistor) and the MOSFET (metal-oxide semiconductor field-effect transistor). We will only be discussing FET here. Both concepts are different but the overall use of the transistor is similar.

A MOSFET, or simply MOS transistor is modeled as a 3-terminal device that acts like a voltage-controlled resistance. As suggested by the figure below, an input voltage applied to one terminal controls the resistance between the remaining two terminals. In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”).

NMOS

There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used in the controlled resistance. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in the figure below. The terminals are called gate, source, and drain. Note that the “gate” of a MOS transistor is not a “logic gate,” though it does “gate” the flow of current between the other two terminals. As you might guess from the orientation of the circuit symbol, the drain is normally at a higher voltage than the source.

The gate of a MOS transistor has a very high impedance. That is, the gate is separated from the source and the drain by an insulating material with a very high resistance. However, the gate voltage creates an electric field that enhances or retards (“gates”) the flow of current between source and drain. This is the “field effect” in the “MOSFET” name.

Regardless of gate voltage, almost no current flows from the gate to source, or from the gate to drain for that matter. The resistance between the gate and the other terminals of the device is extremely high, well over a megohm in CMOS logic families. The small amount of current that flows across this resistance is very small, well under one microampere (μA), and is called a leakage current.

The MOS transistor symbol itself reminds us that there is no connection between the gate and the other two terminals of the device. However, the gate of a MOS transistor is capacitively coupled to the source and drain, as the symbol might suggest. In high-speed circuits, the power needed to charge and discharge this capacitance on each input-signal transition accounts for a nontrivial portion of a circuit’s power consumption.

CMOS Logic

NMOS and PMOS transistors are used together in a complementary way to form CMOS logic. The simplest CMOS circuit, a logic inverter, requires only one of each type of transistor, connected as shown in the figure below. The power-supply voltage, VDD, typically may be in the range 1–6 V; in some CMOS logic families it may be set to 5.0 V for compatibility with the legacy TTL family.

Check out the CMOS Inverter Built Below

Another way to visualize CMOS operation uses switches. As shown in the figure below, the n-channel (bottom) transistor is modeled by a normally-open switch, and the p-channel (top) transistor by a normally-closed switch. Applying a HIGH voltage “pushes” each switch to the opposite of its normal state, as shown in (b).

CMOS Inverter

The switch model gives rise to a way of drawing CMOS circuits that makes their logical behavior more readily apparent. As shown in the next figure below, different symbols are used for the p- and n-channel transistors to reflect their logical behavior. The n-channel transistor (Q1) is switched “on,” and current flows between source and drain, when a HIGH voltage is applied to its gate; this seems natural enough. The p-channel transistor (Q2) has the opposite behavior. It is “on” when a LOW voltage is applied; the inversion bubble on its gate indicates this inverting behavior.

CMOS NAND Gate

The figure below shows a 2-input CMOS NAND gate. If either input is LOW, the output Z has a low-impedance connection to. VDD through the corresponding “on” p-channel transistor, and the path to ground is blocked by the corresponding “off” n-channel transistor. If both inputs are HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground. 

CMOS NOR GATE

The figure below shows a CMOS NOR gate. If both inputs are LOW, then the output Z has a low-impedance connection to VDD through the “on” p-channel transistors, and the path to ground is blocked by the “off” n-channel transistors. If either input is HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground.