The symbol for an ALU is shown above
Design all operations of the ALU independently. There are a total of 8 operations. All operations are 4 bit.
F = A +B with Carry in and Carry out
F = B-A with Borrow In and Borrow out
F = A - B with Borrow In and Borrow out
F = 2 x A with a flag for overflow
F = A / 2 with a flag for overflow
F = A x B with overflow
F = A XOR B (Bitwise XOR)
F = A < B (F = 1 if true, F=0 otherwise)
Task 2 is to design a very basic control unit that will allow you to switch between operations. Given any input A, B, and control signal S, build a circuit that will select between the operations and perform the correct operation on the input(s). The output of the operation should be sent to Output F. The table below describes the ALU operations in detail.
After completing your design for control,
Implement your complete ALU design in the circuit simulator.
Implement each module from task1 and save the file.
Create a subcircuit for each module in task 1.
Implement a new circuit using your basic control unit and the subcircuit modules to realize the final ALU.
NOTE: To test your circuit use a ROM and a counter. The ROM should store all the inputs needed in a hex file. Use the counter to cycle through all the ROM data and make sure you are getting the correct outputs for each ROM address.
for example,
The instruction below adds 0100 and 0011 with no carry in
S=011, XIN= 0, A=0100, B=0011 could be stored as an 12 bit binary number in a rom as SXAB.
SXAB -> 001001000011 (base-2)
= 0010 0100 0011(base-2)
= 243 (base-16) (You can represent it in hex if you want)
The output from the above command would be
F = 0111 , Z = 0, V = 0, C = 0
Using this method, you can easily test your ALU with a single ROM design. Use data similar to above to test a large amount of cases. You then use the counter on the ROM to loop through and check each output to make sure your ALU is working properly.
Implement the ALU in Verilog (alu.v)
Build a test bench to test your alu (alu_tb.v)
All your design work in a single pdf. This includes tables, diagrams, drawings, etc.
all circuit files from task 1
all circuit files from task 2
alu.v and alu_tb.v