The objectives of this lab are to get test out the basics of Flip Flops. You will also be given a design problem to test your knowledge FSM knowledge. In addition, you will get practice in creating subcircuits.
WARNING: In this lab you are creating subcircuits. Subcircuits sometimes have problems saving so it's a good idea to save your circuits as a text file before creating and using your subcircuits.
In Homework 5 problem 3. Your job was to convert between different Flip Flops.
In your simulator, build the circuits for problems 3a, 3b, and 3c.
Write down the full truth table for all of your designs and confirm that they do indeed match the Flip Flop you are trying to create.
You will need all your work and a screenshot of your circuits for submission.
In Homework 4, you've all built a BCD to 7 Segment Decoder circuit. It should have been named seven.txt. If you did it incorrectly, now is your chance to fix it since you will need it here.
Turn your circuit from Homework 4 into a subcircuit
Load it into the simulator
Confirm it works before you start
You can find Labeled Node under Draw > Outputs and Labels
Attach a Labeled node to each of the 4 inputs (The BCD inputs)
Attach a Labeled node to each of 7 outputs (The 7 segment Decoder inputs)
Click on File > Create Subcircuit
Organize the inputs and outputs so inputs are on the left and outputs are on the right. (You can increase the width and height if you need more room)
use BCD2Seven as the name of your Sub Circuit
Click Ok
Test your sub circuit
Start a new empty circuit
Click on Draw > Active Building Blocks > Add Subcircuit Instance.
You should be able to draw your circuit now.
Add a 7 segment display and test your circuit by changing the inputs
You will need all your work and a screenshot of your circuit before creating the sub circuit for submission.
Design a 4-bit binary counter that counts from 0 to 9 and loops if an input UP is HIGH. If input UP is low the counter should count backwards from 9-0 and loop. Hint: Some students may find that you need to design using a 5-bit K Map. While this is certainly possible, you can think of the problem a little bit and think about how the bits change in patterns. In this way, you could design a 3-bit up/down counter, if you see any patterns, you should be able to easily expand to a 4-bit up/down counter.
Draw the state diagram
Draw the ASM chart
Write the State Table
Draw all kmaps and simplifications used to design the circuit.
Create a subcircuit with your counter
Name your counter UpDownCounter
It should only have the input UP and the input for the CLOCK signal.
It should also have a 4 bit output
Test your circuit
Draw your UPDownCounter subcircuit.
Draw your BCD2Seven subcircuit and connect it's inputs to the outputs of your Counter
Connect a 7 segment display to the output of your BCD2Seven subcircuit
Does your counter perform as it should? Describe the performance of your counter? How do you use it?
Is this a Mealy or Moore Machine?
You will need all your work and a screenshot of your circuit before it's turned into a subcircuit for submission.
Start investigating the FPGAs in the Lab
Can you find the manual for the FPGA online?
Investigate Vivado (installed on the lab computers)
Are you able to find information on Vivado online?
Can you deploy some simple Verilog Designs from the Verilog Quickstart Guide or the examples given in class? For example deploy a simple Inverter.
Describe the process to deploy the verilog code to the FPGA.
Include any necessary pictures, figures, and diagrams needed
Where you succesfful in your deployment? If not, make sure you understand this process by the next lab
Submit all truth tables, diagrams, next state tables, K Maps and screenshots from each section. For section 5, describe the process needed to design a circuit and deploy onto an FPGA in the lab.