ROM & RAM -RAM Discussion

ROM

A read-only memory (ROM) is a combinational circuit with n inputs and b outputs, as shown in the figure below. The inputs are called address inputs and are traditionally named A0, A1, …, An–1. The outputs are called data outputs and are typically named D0, D1, …, Db–1.

There are different kinds of Commercial ROMS

RAM

The name read/write memory (RWM) is given to memory arrays in which we can store and retrieve information at any time. All of the RWMs used in digital systems nowadays are random-access memories (RAMs), which means that the time it takes to read or write a bit is independent of the bit’s location in the RAM. From this point of view, ROMs are also random-access memories, but the name “RAM” is generally used only for read/write random-access memories.

Static RAM (SRAM) & Dynamic RAM (DRAM)

In a static RAM (SRAM) (“S-ram”), once a word is written at a location, it remains stored as long as power is applied to the chip, unless the same location is written again. In a dynamic RAM (DRAM) (“D-ram”), the data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears.

Most RAMs lose their memory when power is removed; they are a form of volatile memory. Some RAMs retain their memory even when power is removed; they are called nonvolatile memory. Examples of nonvolatile RAMs are old-style magnetic core memories and modern CMOS static memories in an extra-large package that includes a lithium battery with a 10-year lifetime.

Structure of a 2^n x b RAM

Static RAM - The SRAM Cell

Each bit of memory (or SRAM cell) in a static RAM has the same functional behavior as the circuit in the figure below. The storage device in each cell is a D latch. When a cell’s SEL_L input is asserted, the stored data is placed on the cell’s output, which is connected to a bit line. When both SEL_L and WR_L are asserted, the latch is open and a new data bit is stored.

Static RAM (SRAM) Circuit

SRAM cells are combined in an array with additional control logic to form a complete static RAM, as shown for an 8 × 4 SRAM in the figure below. A decoder on the address lines selects a particular row of the SRAM to be accessed at any time.