L4: Types of Architecture

Processor architecture defines how a computer's CPU processes instructions and manages data. The two main architectures—Von Neumann and Harvard—differ in how they handle instructions and data. Additionally, Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC) impact processor performance in different ways. Understanding these architectures is crucial in analyzing modern computing efficiency, from general-purpose computers to embedded systems.

Learning Objectives

✅ I can describe the key features of Von Neumann and Harvard architectures.
✅ I can compare the advantages and disadvantages of each architecture.
✅ I can explain the differences between RISC and CISC architectures.
✅ I can analyze the impact of processor architecture on performance and efficiency.

Key Terminology

Architecture – The design and structure of a computer processor.
Von Neumann Architecture – A processor design where instructions and data share the same memory and buses.
Harvard Architecture – A processor design where instructions and data are stored in separate memory and use different buses.
Shared Bus – A single bus used for both data and instructions in Von Neumann architecture.
Separate Bus – Distinct buses for data and instructions in Harvard architecture.
RISC (Reduced Instruction Set Computing) – A processor design that uses a small, optimized set of simple instructions.
CISC (Complex Instruction Set Computing) – A processor design that uses a large set of complex instructions to perform tasks.
Pipelining – A technique that improves processing efficiency by overlapping the Fetch-Decode-Execute cycles of multiple instructions.
Instruction Cycle – The process of fetching, decoding, and executing an instruction.
Memory Bottleneck – A limitation in Von Neumann architecture caused by the shared bus for instructions and data.
Parallel Processing – The simultaneous execution of multiple instructions, used in modern processor architectures.
Control Unit (CU) – Directs the flow of data and instructions in a processor.
Latency – The delay before a process starts executing, often due to memory or processing constraints.
Throughput – The number of instructions a processor can execute in a given time.
Hybrid Architecture – A combination of different architectures to balance performance and efficiency.

Key Ideas

Von Neumann Architecture

Instructions and data share the same memory and buses.
Simpler and more cost-effective to implement.
A single bus causes a memory bottleneck, slowing down processing when data and instructions compete for bandwidth.
Commonly used in general-purpose computers, such as PCs, laptops, and servers.

Harvard Architecture

Instructions and data have separate memory and buses, eliminating memory bottlenecks.
More complex and expensive to design.
Enables faster access to data and instructions.
Commonly used in embedded systems, such as microcontrollers, DSPs (Digital Signal Processors), and avionics systems.

Harvard & Von Neumann Architectures

Von Neumann Architecture

Instructions and data share the same memory and buses.
Simpler and more cost-effective to implement.
A single bus causes a memory bottleneck, slowing down processing when data and instructions compete for bandwidth.
Commonly used in general-purpose computers, such as PCs, laptops, and servers.

Harvard Architecture

Instructions and data have separate memory and buses, eliminating memory bottlenecks.
More complex and expensive to design.
Enables faster access to data and instructions.
Commonly used in embedded systems, such as microcontrollers, DSPs (Digital Signal Processors), and avionics systems.

Comparison of Von Neumann and Harvard Architectures

RISC & CISC Instruction Sets

RISC (Reduced Instruction Set Computing)

Uses a small set of simple instructions, designed for fast execution.
Uniform instruction size simplifies processing.
Optimized for pipelining, improving efficiency.
Examples: ARM processors used in mobile devices, Raspberry Pi, and embedded systems.

CISC (Complex Instruction Set Computing)

Uses a large and complex set of instructions, where a single instruction can perform multiple tasks.
More powerful but less optimized for pipelining.
Examples: x86 processors used in desktops and laptops.

Application Areas

Von Neumann Architecture – Used in most general-purpose computing (PCs, laptops, servers).
Harvard Architecture – Found in systems requiring high throughput and real-time processing (e.g., aviation systems, microcontrollers, and DSPs).
RISC Processors – Common in mobile and embedded devices where efficiency is key.
CISC Processors – Used in desktops, laptops, and enterprise computing for powerful, multi-purpose processing.

Impact of Architecture on Performance

Reducing memory bottlenecks increases speed and efficiency.
Pipelining improves processing by allowing instructions to be executed simultaneously.
Parallel processing further enhances speed in modern multi-core processors.
Choice of architecture depends on the specific needs of the application (e.g., cost, speed, power consumption).

Future Trends

Hybrid Architectures: Combining elements of RISC and CISC for a balanced approach (e.g., modern x86 processors include RISC-like optimizations).
Multi-core and parallel processing: Improving performance by allowing multiple instructions to execute at once.
Edge computing and AI acceleration: Processors designed for specific workloads, such as AI, machine learning, and IoT devices.

Von Neumann & Harvard

This video highlights the differences between Von Neumann and Harvard architectures, as well as RISC and CISC, explaining their unique features and use cases.

Lesson Flashcards

Guided Note Taking

Create your own revision notes using the following prompts:

Summarize Von Neumann and Harvard architectures in your own words.
List the advantages and disadvantages of both architectures.
Compare RISC and CISC processors in a short table.
Explain why Harvard architecture is used in embedded systems.
Give two examples of modern processors that use each architecture type.

Comprehension Questions

What is the key difference between Von Neumann and Harvard architecture?
Why is RISC preferred in mobile devices and embedded systems?
How does pipelining improve processor efficiency?
Explain why Von Neumann architecture can suffer from memory bottlenecks.

Activities

Architecture Diagrams: Draw labeled diagrams of Von Neumann and Harvard architectures. Annotate them with the key differences in memory and bus usage.
RISC vs. CISC Table: Work in pairs to create a table comparing RISC and CISC architectures. Share your findings with another pair.
Case Study: Research a real-world device (e.g., smartphone, gaming console) and identify whether it uses RISC or CISC processors. Present your findings to the class.

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