1. Здесь собраны рекомендации по разводке дифф. пар. Из разных источников. Иногда рекомендации противоречат друг другу.
1.1. Разводка дорожек по плате.
1.1.1. 9 дюймов [1].
1.1.2. Короткие, насколько возможно [1,2].
1.1.3. 11 inches [4].
1.1.4. use as few bends as possible[4].
1.2. Разное
1.2.1. The USB 3.0 standard introduces two additional data signal pairs for the Super Speed link. These two pairs are running at 5 Gbit/s and are fully compliant to the PCI Express Base Specification [6].
1.2.2. USB 3.1 & USB 2.0 differential trace MUST use different layer to avoid cross routing[1,2].
1.2.3. When implementing a through-hole receptacle (like a USB Standard-A), TI recommends making high speed differential signal connections to the receptacle on the bottom layer of the PCB[3].
1.2.4. Also, do not put any metal between all SuperSpeed signal pair pins on every layer when using receptacles with pins stabbing the PCB [5]
1.2.5. For the shielding of USB connector (shielding of USB cables), AC isolation to the ground (such as proper value of inductor, instead of connecting the cable shield directly to the PCB ground plane). [5]
1.2.6. For the Vbus trace, it’s suggested to insert a ferrite bead.[5]
1.2.7. anti-pad diameter 30 mils [3].
1.2.8. TI recommends placing vias as close as possible to the SoC[3].
1.2.9. TI recommends voiding the SMD mounting pads of the reference plane by 100%. This void should be at least two PCB layers deep. И вырезать сплошняком [3].
1.2.10. Place ESD and EMI protection devices as close as possible to the connector.[3].
1.2.11. Incorporate 60% voids under the ESD/EMI component signal pads to reduce losses [3].
1.2.12. Use 0402 0-Ω resistors for common-mode filter (CMF) no-stuff options because larger components will typically introduce more loss that the CMF itself [3].
1.2.13. If vias are needed to transition to the CMF layer, ensure that the vias are as close as possible to the CMF[3].
1.2.14. You can swap the SSTX and SSRX pairs but not the USB2 (D+/D-) pair. This is because, during SuperSpeed enumeration, certain training sequences (called TSEQs) are sent and the D10.2 symbol in this is used to detect if lane polarity inversion is done (refer to section 6.4.2 of the USB 3.0 spec). However, such lane inversion detection is not done in USB 2.0 enumeration. This inversion is recommended if your design will cause SSTX+ and SSTX- (or the RX pairs) to cross each other. Then you can swap these pins to avoid this crossing
1.3. The AC coupling Capacitor
1.1.1. 0402 is recommended, 0.1uF[1,2].
1.1.2. The AC coupling Capacitor should be placed by closing to Connector[1,2].
1.1.3. Keep the overall routing of AC coupling capacitors + CMF + ESD protection as short and as close as possible to the connector [3].
1.1.4. Place any required signal pair AC coupling capacitors on the protected side of the CMF and as close as possible to the CMF[3].
1.2. Раположение на одной плате
1.2.1. Длина дорожек на матиринской плате9 –inch [1].
1.2.2. Схема соединений SS линий рис 3.4 [1].
1.3. Расстояния в дифф.паре.
1.3.1. 6/6 и 7/8 mils [1].
1.4. Расстояние между разными дифф. парами
1.4.1. 20 mils or 4h[1].
1.4.2. Maximize differential pair-to-pair spacing when possible[3].
1.5. Расстояние между дифф. парами и медленными сигналами
1.5.1. 20 mils[1].
1.5.2. 30 mils [3]
1.5.3. 8 mils [4]
1.6. Расстояние между дифф. парами и быстрыми осциллирующими сигналами
1.6.1. 50 mils [3].
1.6.2. Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals[3].
1.7. Via
1.7.1. Number of vias allowed on USB3 differential trace (Total) 2 Vias [3]
1.7.2. Number of vias allowed on each USB2.0 differential trace (Total) 4 Vias () [3]
1.8. Ground via
1.8.1. Близко к сигнальным via и не менее 2 шт. Пространство менее 50 mils. И сшивающие via рекомендуют [1].
1.8.2. Place these stitching vias symmetrically within 200 mils(center-to-center, closer is better) of the signal transition vias [3].
1.8.3. The distancebetween the signal and ground vias should be at least 40 mils (по центрам) [4]
1.9. Разность длин
1.9.1. SS 5 mils, USB 2.0 50 mils[1].
1.9.2. When matching the intra-pair length of the high-speed signals, add serpentine routing to match the lengths as close to the mismatched ends as possible[3].
1.9.3. Adjust the Hi-Speed signal trace lengths near the USB receptacle, if necessary [4].
1.9.4. Make adjustments for SS Rx signal trace lengths near the USB receptacle, and adjustments for SS Tx signal trace lengths near the device, if necessary.[4].
1.9.5. Each segment of a differential pair connection needs to be matched individually [6]
1.9.6. If the space between the pads permits, try to add a small loop to the shorter trace. This is the preferred solution for matching the length difference as opposed to creating a serpentine trace [6].
1.9.7. Max trace length skew between RX and TX data pairs 240mm [6]
2. GND
2.1. TI does not recommend high-speed signal references to power planes [3].
2.2. Make the differential signal trace GND plane via holes as more as possible to keep GND plane solid with adjacent GND layer [1,2].
2.3. Ensure that high-speed differential signals are routed ≥90 mils from the edge of the reference plane[3].
2.4. Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided [3].
2.5. A lot of reference schematics for mixed signal integrated circuits (e.g. ADC) propose a split ground approach [6].
2.6. The virtual split approach does not split the analogue and digital ground in the schematic diagram. In the layout, the two ground domains are not electrically split. The trick is to implement the layout as if there is an imaginary separation between the analogue and digital ground [6].
3. Ширина дорожки питания для BC1.2 (1.5A)
3.1. 60 mils[1].
4. Кварц
4.1. Расстояние меньше 10 mm, образец разводки рис 2.12 [1].
4.2. Дорожки не проводить под IC [1].
4.3. Also, make sure that there is a solid ground plane under the crystal trace [4].
5. Питание
5.1. For the main current paths, keep their traces short, direct and wide[2].
5.2. Keep the connect feedback network behind the output capacitors[2].
5.3. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND[2].
5.4. For the same voltage level’s analog power and digital power, a ferrite bead should be added in between for noise filtering.[5]
Список источников.
1. USB 3.0 HubDesignGuide_211.pdf
2. USB 3.1 HubDesign Guide_100 (1).pdf
3. spraar7f.pdf
4. AN91378_001-91378_0A_V (1).pdf
5. AN310-P.pdf
6. layout_design_guide.pdf