2023
Conference
[A-SSCC'23][Distinguished Design Award][Invited to CICC2024] Y. Lu, X. Zhang, B. Wang, and T. Kim, "SESOMP: A Scalable Energy-Efficient Self-Organizing Map Processor with Compute-In-Memory and Dead Neuron Pruning," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347932. [Paper]
[A-SSCC'23] X. Zhang, V. Sharma, Y. Lu, Y. Jo, and T. Kim, "A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SAM-Basd Digital Compute-In-Memory Macro for Accelerating CNNs," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347952. [Paper]
[A-SSCC'23] D.-H. Yoon, J. He, K.-H. Baek, Y. Choi, J.-H. Choi, and T. Kim, "A Time-based PAM-4 Transceiver using Single Path Decoder and Fast-Stochastic Calibration Techniques," IEEE Asian Solid-State Circuits Conference, Nov. 2023, pp. 1-3, doi: 10.1109/A-SSCC58667.2023.10347939. [Paper]
[SOVC'23] J. Mu, C. Yu, T. Kim, and B. Kim, "A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations," IEEE Symposium on VLSI Circuits, June 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185162 [Paper]
[NEWCAS'23] B. An, X. Zhang, A. T. Do, and T. Kim, "Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory," IEEE Interregional NEWCAS Conference, June 2023, pp. 1-5, doi: 10.1109/NEWCAS57931.2023.10198038 [Paper]
[ISCAS'23][Invited to TCAS-II] X. Zhang*, Y. Lu*, B. Wang, and T. Kim, "A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration," IEEE International Symposium on Circuits and Systems, May 2023 [Paper] (* equally contributed authors)
[ISCAS'23] J. He, D.-H. Yoon, and T. Kim, "An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory," IEEE International Symposium on Circuits and Systems, May 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181848 [Paper]
[ISCAS'23] Z. Wei, J. Mu, Y. Zheng, T. Kim, and B. Kim, "A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing," IEEE International Symposium on Circuits and Systems, May 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181454. [Paper]
[ISCAS'23] Q. Zang, W. L. Goh, L. Lu, C. Yu, J. Mu, T. Kim, B. Kim, D. Li, and A. T. Do, "282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing," IEEE International Symposium on Circuits and Systems, May 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181435 [Paper]
[CICC'23] Y.-J. Jo, B. P. Yap, D.-H. Yoon, H. Kim, Y. Zheng, and T. Kim, "DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi: 10.1109/CICC57935.2023.10121213 [Paper]
[CICC'23] C. Yu, J. Mu, K. Chai, T. Kim, and B. Kim, "A Continuous-Time Ising Machine Using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi: 10.1109/CICC57935.2023.10121286. [Paper]
[CICC'23][Invited to SSC-L] Y. Su, T. Kim, and B. Kim, "A Reconfigurable Ising Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions," IEEE Custom Integrated Circuits Conference, Apr. 2023, pp. 1-2, doi: 10.1109/CICC57935.2023.10121303 [Paper]
Journal
[SSC-L'23][Invited] Y. Su, T. Kim, and B. Kim, "A Reconfigurable CMOS Ising Machine with Three-Body Spin Interactions for Solving Boolean Satisfiability with Direct Mapping," IEEE Solid-State Circuits Letters, vol. 6, pp. 221-224, doi: 10.1109/LSSC.2023.3303332 [Paper]
[JSSC'23] C. Yu, J. Mu, Y. Su, K. Chai, T. Kim, and B. Kim, "A Time-Domain Wavefront Computing Accelerator with a 32×32 Reconfigurable PE Array," IEEE Journal of Solid-State Circuits, vol. 58, pp. 2372-2382, August 2023 [Paper]
[TCAS-II'23][Invited] X. Zhang*, Y. Lu*, B. Wang, and T. Kim, "A Digital Bit-Reconfigurable Versatile Compute-In-Memory Macro for Machine Learning Acceleration," IEEE Transactions on Circuits and Systems-II, vol. 70, pp. 1744-1748, May 2023 [Paper] (* equally contributed authors)
[TCAS-I'23] Y. Chen, J. Mu, H. Kim, L. Lu, and T. Kim, "BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 2016-2027, May 2023 [Paper]
[SSC-L'23] [Invited] J. E. Kim*, D.-H. Yoon*, J. Song, K.-H. Baek, J.-H. Choi, and T. Kim, "A 6 Gbps PAM-3 Transceiver with Background Time-Varying Offset Sensing and Compensation," IEEE Solid-State Circuits Letters, vol. 6, pp. 85-88, 2023 [Paper] (* equally contributed authors)
[SSC-L'23] [Invited] Y.-J. Jo*, X. Zhang*, J. Liu, J. Zhou, Y. Zheng, and T. Kim, "Transposable 9T-SRAM Computation-In-Memory for On-Chip Learning with Probability-Based Single-Slope SAR Hybrid ADC for Edge Devices," IEEE Solid-State Circuits Letters, vol. 6, pp. 81-84, 2023 [Paper] (* equally contributed authors)
[TCAS-I'23] H. Kim, J. Mu, C. Yu, T. Kim, and B. Kim, "A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 1580-1590, Apr. 2023 [Paper]
[JSSC'23] Y. Lu, V. L. Le, and T. Kim, "A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN," IEEE Journal of Solid-State Circuits, vol. 58, pp. 530-542, Feb. 2023 [Paper]
[TCAS-I'23] X. Zhang, B. An, and T. Kim, "A Robust Time-based Multi-level Sensing Circuit for Resistive Memory," IEEE Transactions on Circuits and Systems-I, vol. 70, pp. 340-352, Jan. 2023 [Paper]
