2010
Conference
[APCCAS'10] Q. Li and T. Kim, “A 9T Subthreshold SRAM Bitcell with Data-independent Bitline Leakage for Improved Bitline Swing and Variation Tolerance,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 260-263, Dec. 2010 [Paper]
Journal
[MRJ'10] [Invited] J. Keane, T. Kim, X. Wang, and C. Kim, "On-Chip Reliability Monitors for Measuring Circuit Degradation," Microelectronics Reliability Journal, Vol. 50, pp. 1039-1053, Aug. 2010 [Paper]
[TVLSI'10] J. Keane, T. Kim, and C. Kim, “An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation,” IEEE Trans. on VLSI Systems, Vol. 18, No. 6, pp. 947-956, June 2010 [Paper]
2006 ~ 2009
Conference
[CICC'09] Tae-Hyoung Kim, Wei Zhang, and Chris Kim, “An SRAM Reliability Test Macro for Fully-Automated Statistical Measurements of Vmin Degradation,” IEEE Custom Integrated Circuits Conference, pp. 231-234, Sep. 2009 [Paper]
[ICCAD'08] John Keane, Tae-Hyoung Kim, and Chris Kim, ”Silicon Odometers: On-Chip Test Structures for Monitoring Reliability Mechanisms and Sources of Variation,” Workshop on Test Structure Design for Variability Characterization in Conjunction with IEEE International Conference on Computer-Aided Design, Nov. 2008 [Paper]
[CICC'08] [AMD/CICC Student Scholarship Award] Tae-Hyoung Kim, Jason Liu, and Chris Kim, “A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode,” IEEE Custom Integrated Circuit Conference, pp. 407-410, Sep. 2008 [Paper]
[ISLPED'08] Pulkit Jain, Tae-Hyoung Kim, John Keane, and Chris Kim, “A Multi-Story Power Delivery Technique for 3D Integrated Circuits,” IEEE International Symposium on Low Power Electronics and Design, pp. 57-62, Aug., 2008 [Paper]
[ISCAS'08] [Invited] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “Circuit Techniques for Ultra-Low Power Sub-threshold SRAMs,” IEEE International Symposium on Circuits and Systems, pp. 2574-2577, May 2008 [Paper]
[CICC'07] Tae-Hyoung Kim, Jason Liu, and Chris Kim, “An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement,” IEEE Custom Integrated Circuits Conference, pp. 241-244, Sep. 2007 [Paper]
[ISLPED'07] John Keane, Tae-Hyoung Kim, and Chris Kim, “An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation,” IEEE International Symposium on Low Power Electronics and Design, pp. 189-194, Aug. 2007 [Paper]
[SOVC'07] [DAC/ISSCC Design Contest Winner][Invited to JSSC] Tae-Hyoung Kim, Randy Persaud, and Chris Kim, “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Symposium on VLSI Circuits, pp. 122-123, June 2007 [Paper]
[ISSCC'07] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual-Ground Replica Scheme,” IEEE International Solid State Circuits Conference, pp. 330-606, Feb. 2007 [Paper]
[ISLPED'06] Tae-Hyoung Kim, Hanyong Eom, John Keane, and Chris Kim, “Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design," IEEE International Symposium on Low Power Electronics and Design, pp. 127-130, Oct. 2006 [Paper]
[DAC'06] John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin Sapatnekar, and Chris Kim, “Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing,” IEEE Design Automation Conference, pp. 425-428, July, 2006 [Paper]
Journal
[JSSC'09] Tae-Hyoung Kim, Jason Liu, and Chris H. Kim, “A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode,” IEEE Journal of Solid State Circuits, Vol. 44, No. 6, pp. 1785-1795, June 2009 [Paper]
[TVLSI'08] John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin Sapatnekar, and Chris Kim, “Stack Sizing for Optimal Current Drivability in Subthreshold Circuits,” IEEE Trans. on VLSI Systems, Vol. 16, No. 5, pp. 598-602, May 2008 [Paper]
[JSSC'08] [Invited] Tae-Hyoung Kim, Randy Persaud, and Chris Kim, “Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits,” IEEE Journal of Solid State Circuits, Vol. 43, No. 4, pp. 874-880, Apr. 2008 [Paper]
[JSSC'08] Tae-Hyoung Kim, Jason Liu, John Keane, and Chris Kim, “A 0.2V, 480kb Subthreshold SRAM with 1k Cells per Bitline for Ultra-Low Voltage Computing,” IEEE Journal of Solid State Circuits, Vol. 43, No. 2, pp. 518-529, Feb. 2008 [Paper]
[TVLSI'07] Tae-Hyoung Kim, John Keane, Hanyong Eom, and Chris Kim, “Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design,” IEEE Trans. on VLSI Systems, Vol. 15, No. 7, pp. 821-829, July, 2007 [Paper]
2000 ~ 2005
Conference
[ISCAS'05] Tae-Hyoung Kim, Uk-Rae Cho, and Hyun-Geun Byun, “A 1.2V Multi Gb/s/pin Memory Interface Circuits with High Linearity and Low Mismatch,” IEEE International Symposium on Circuit and System, pp.1847-1850, May, 2005
[AP-ASIC'04] [Invited to IEICE] Tae-Hyoung Kim, Uk-Rae Cho, and Hyun-Geun Byun, “A High Resolution, Wide Range Digital Impedance Controller for High-Speed SRAM Interface,” IEEE Asia-Pacific Conference on Advanced System IC (AP-ASIC), pp. 120-123, Aug., 2004
[ISSCC'03] [Invited to JSSC] Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, et al., “A 1.2V 1.5Gbps 72M DDR3 SRAM,” IEEE International Solid State Circuits Conference (ISSCC), pp. 300-494, Feb., 2003
[KCS'01] Tae-Hyoung Kim, Woong Joo, Jun-Jey Sung, Seung-Bin You, and Suki Kim, “An 8-Bit 40MSamples/s Low Power Folding & Interpolating ADC,” IEEK Korea Conference on Semiconductor (KCS), Feb. 2001
[AP-ASIC'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Woong Joo, Seung-Bin You, and Suki Kim, “A 10-bit 40Msamples/s Cascading Folding & Interpolating A/D Converter with Wide Range Error Correction,” IEEE Asia-Pacific Conference on Advanced System IC (AP-ASIC), pp. 57-60, Aug., 2000
[KCS'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Shin-Il Lim, and Suki Kim, “A 10-Bit, 40MSamples/s, Fully Nyquist Rate and Folding & Interpolating ADC with a Cascading Architecture,” IEEK Korea Conference on Semiconductor, Jan., 2000
Journal
[IEICE'05] [Invited] Tae-Hyoung Kim, Kwang-Jin Lee, Uk-Rae Cho, and Hyun-Geun Byun, “A High Resolution, Wide Range Digital Impedance Controller,” IEICE Trans. on Electronics, Vol. E88-C, pp. 1723-1725, Aug. 2005
[ETRI'05] [ETRI Journal Paper of the Year] Kwang-Jin Lee, Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun, and Suki Kim, “Voltage-mode 1.5Gbps Interface Circuits for Chip-to-Chip Communication,” ETRI Journal, Vol. 27, Number 1, pp. 81-88, Feb., 2005
[JSSC'03] [Invited] Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, et al., “A 1.2V 1.5Gbps 72M DDR3 SRAM,” IEEE Journal of Solid State Circuits (JSSC), Vol. 38, pp. 1943-1951, Nov., 2003
[JKPS'02] Mingi Kim, Tae-Hyoung Kim, Woong Joo, et al., “Low Power, 8-bit 40Msamples/s A/D Converter with a Wide Range Error Correction Scheme,” Journal of Korea Physics Society, Vol. 40, No. 1, pp. 11-16, Jan., 2002
[ASIC'00] Tae-Hyoung Kim, Jun-Jey Sung, Soo-Hwan Kim, Shin-Il Lim, and Suki Kim, “A 10-bit, 40-MSamples/s, Folding & Interpolating ADC with Wide Range Error Correction,” Journal of the Research Institute of ASIC Design, Aug. 2000
