2016
Conference
[A-SSCC'16] [Invited to Student Design Contest] A. T. Do, S. M. A. Zeinolabedin and T. Kim, "A 0.3 pW/Access 8T Data-Aware SRAM Utilizing Column-based Data Encoding for Ultra-Low Power Applications," IEEE Asian Solid-State Circuits Conference, pp. 173-176, Nov. 2016 [Paper]
[A-SSCC'16] A. Das, Y. Gao and T. Kim, "An Isolated PoR Based Pulse Generator for TEG Energy Harvesting with Minimum Startup of 150 mV and Maximum Series Resistance of 600 Ω," IEEE Asian Solid-State Circuits Conference, pp. 297-300, Nov. 2016 [Paper]
[APCCAS'16] M. Aung and T. Kim, "Self-Contained Built-In-Self-Test/Repair Transceivers for Interconnects in 3DICs," IEEE Asia Pacific Conference on Circuits and Systems, pp. 640-641, Oct. 2016 [Paper]
[APCCAS'16] K. G. Jayaraman, K. Rawy, and T. Kim, "A 0.6-V Power Efficient Digital LDO with 99.7% Current Efficiency Utilizing Load Current Aware Clock Modulation for Fast Transient Response," IEEE Asia Pacific Conference on Circuits and Systems, pp. 103-106, Oct. 2016 [Paper]
[ICCE-Asia'16] [Invited] T. Kim, D. Trang, and I. Chang, "Design of Energy Efficient Ultra-low Voltage SRAMs for Internet-of-Things Applications," IEEE International Conference on Consumer Electronics Asia, Oct. 2016
[VLSI-SoC'16] M. Jayakrishnan, A. Chang, and T. Kim, "Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience," IFIP/IEEE International Conference on Very Large Scale Integration, pp. 1-6, Oct. 2016 [Paper]
[ESSCIRC'16] N. Narasimman and T. Kim, "A 0.3 V, 49 fJ/Conv.-step VCO-based Delta Sigma Modulator with Self-compensated Current Reference for Variation Tolerance," IEEE European Solid-State Circuits Conference, pp. 237-240, Sept. 2016 [Paper]
[ESSCIRC'16] Z. C. Lee*, M. S. M. Siddiqui*, Z. H. Kong, and T. Kim, "An 8T SRAM with BTI-Aware Stability Monitor and Two-Phase Write Operation for Cell Stability Improvement in 28-nm FDSOI," IEEE European Solid-State Circuits Conference, pp. 437-440, Sept. 2016 (*equally contributed) [Paper]
[ESSCIRC'16] K. Rawy, F. K. George, D. Maurath, and T. Kim, "A 96.2% Efficiency Time-based Energy-Harvesting MPPT with 5.1µW Power Consumption and 10-µA to 1-mA Tracking Range," IEEE European Solid-State Circuits Conference, pp. 503-506, Sept. 2016 [Paper]
[SOVC'16] [Low Power Design Contest Award at ISLPED] S. M. A. Zeinolabedin*, A. T. Do*, D. Jeon, D. Sylvester, and T. Kim, "A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS," IEEE Symposium on VLSI Circuits, pp. 32-33, June 2016 (*equally contributed) [Paper]
[SOVC'16] S. Oh, N. L. Ba, S. Bang, J. Jeong, D. Blaauw, T. Kim, and D. Sylvester, "A 260µW Infrared Gesture Recognition System-on-Chip for Smart Devices," IEEE Symposium on VLSI Circuits, pp. 228-229, June 2016 [Paper]
[ISCAS'16] N. Narasimman and T. Kim, "An Ultra-Low Voltage, VCO-Based ADC with Digital Background Calibration," IEEE International Symposium on Circuits and Systems, pp. 1458-1461, May 2016 [Paper]
[ISCAS'16] W.-G. Ho, N. P. Srinivas, K.-S. Chong, T. Kim, and B.-H. Gwee, "Area-Efficient and Power-Saving 1K-Byte Transmission-Gated Non-Imprinting High-Speed Erase (TNIHE) SRAM," IEEE International Symposium on Circuits and Systems, pp. 698-701, May 2016 [Paper]
Journal
[TCAS-I'16] S. Zeinolabedin, J. Zhou, X. Liu, and T. Kim, "A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression," IEEE Transactions on Circuits and Systems-I , Vol. 63, pp. 1690-1700, Oct. 2016 [Paper]
[TVLSI'16] M. Aung, T. Lim, T. Yoshikawa, and T. Kim, "2.31 Gbps/ch Area Efficient Crosstalk Cancelled Hybrid Capacitive Coupling Interconnect for 3D Integration," IEEE Transactions on VLSI Systems, Vol. 24, pp. 2703-2711, Aug. 2016 [Paper]
[JSSC'16] A. Do, Z. Lee, B. Wang, I. Chang, and T. Kim, "0.2 V 8T SRAM with PVT-Aware Bit-line Sensing and Column-based Data Randomization," IEEE Journal of Solid-State Circuits, Vol. 51, pp. 1487-1498, June 2016 [Paper]
[TVLSI'16] B. Wang, Q. Li, and T. Kim, "Read Bitline Sensing and Fast Local Write-back Techniques in Hierarchical Bitline Architecture for Ultra-low Voltage SRAMs," IEEE Transactions on VLSI Systems, Vol 24, pp. 2165-2173, June 2016 [Paper]
Book Chapter
T. Kim and A. M. Thu Linn, "Design of High-Speed Interconnects for 3D/2.5D ICs without TSVs," in Physical Design for 3D Integrated Circuits, CRC Press [Book]
