2012
Conference
[A-SSCC'12] B. Wang, T. Nguyen, A. Do, J. Zhou, M. Je, and T. Kim, "A 0.2V 16Kb 9T SRAM with Bitline Leakage Equalization and CAM-assisted Write Performance Boosting for Improving Energy Efficiency," IEEE Asian Solid-State Circuits Conference, pp. 73-76, Nov. 2012 [Paper]
[ISOCC'12] [Invited] T. Kim, B. Wang, and A. Do, "High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture," International SoC Design Conference (ISOCC), pp. 367-370, Nov. 2012 [Paper]
[ISOCC'12] Z. Lee, K. Ho, Z. Kong, and T. Kim, "NBTI/PBTI-Aware Wordline Voltage Control with No Boosted Supply for Stability Improvement of Half-Selected SRAM Cells," International SoC Design Conference, pp. 200-203, Nov. 2012 [Paper]
[ESSDERC'12] Q. Li, B. Wang, and T. Kim, "A 5.61 pJ, 16 kb 9T SRAM with Single-ended Equalized Bitlines and Fast Local Write-back for Cell Stability Improvement," IEEE European Solid-State Device Research Conference, pp. 201-204, Sept. 2012 [Paper]
[ASQED'12] A. Do, H. Yi, K. Yeo, and T. Kim, "Retention Time Characterization and Optimization of Logic-compatible Embedded DRAM Cells," Asia Symposium on Quality Electronic Design, pp. 29-34, July 2012 [Paper]
[ASQED'12] B. Wang, J. Zhou, and T. Kim, "Maximization of SRAM Energy Efficiency Utilizing MTCMOS Technology," Asia Symposium on Quality Electronic Design, pp. 35-40, July 2012 [Paper]
[ISCAS'12] T. Kim, P. Lu, and C. Kim, "Design of Ring Oscillator Structures for Measuring Isolated NBTI and PBTI," IEEE International Symposium on Circuits and Systems, pp. 1580-1583, May 2012 [Paper]
[IRPS'12] R. Vaddi, V. Pott, J. Lin, and T. Kim, "Design and Analysis of Anchorless Shuttle Nano-electro-mechanical Non-volatile Memory for High Temperature Applications," IEEE International Reliability Physics Symposium, pp. ME.3.1-ME.3.6, Apr. 2012 [Paper]
[ICSIC'12] R. Vaddi, V. Pott, J. Lin, and T. Kim, "Design, Modeling and Simulation of an Anchorless Nano-Electro-Mechanical Nonvolatile Memory for High Temperature Applications," International Conference on Solid-State and Integrated Circuit, pp. 12-17, Mar. 2012
[3DIC'12] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "Design of Capacitive-Coupling-Based Simultaneously Bi-directional Transceivers for 3DIC," IEEE International 3D System Integration Conference, pp. 1-4, Feb. 2012 [Paper]
Journal
[TCAS-II'12] [Special Issue] A. Do, Q. Truc, K. Yeo, and T. Kim, "Sensing Margin Enhancement Techniques for Ultra-low Voltage SRAMs Utilizing Bitline Boosting Current and Equalized Bitline Leakage," IEEE Transactions on Circuits and Systems-II, Vol. 59, pp. 868-872, Dec. 2012 [Paper]
[EDL'12] R. Vaddi, V. Pott, G. Chua, J. Lin, and T. Kim, "Design and Scalability of a Memory Array Utilizing Anchor-free Nano-electro-mechanical Non-volatile Memory Device," IEEE Electron Device Letters, Vol. 33, pp. 1315-1317, Sept. 2012 [Paper]
[EDL'12] V. Pott, R. Vaddi, G. Chua, J. Lin, and T. Kim, "Design optimization of a pulsed-mode electromechanical non-volatile memory," IEEE Electron Device Letters, Vol. 33, pp. 1207-1209, Aug. 2012 [Paper]
[JETCAS'12] M. Aung, E. Lim, T. Yoshikawa, and T. Kim, "Design of Simultaneous Bi-directional Transceivers Utilizing Capacitive Coupling for 3DICs," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, pp. 257-265, June 2012 [Paper]
[TED'12] V. Pott, G. Chua, R. Vaddi, J. Lin, and T. Kim, "The shuttle nano-electro-mechanical non-volatile memory," IEEE Transactions on Electron Devices (TED), Vol. 59, pp. 1137-1143, Apr. 2012 [Paper]
[TCAS-I'12] T. Kim, W. Zhang, and C. Kim, "An SRAM Reliability Test Macro for Fully-Automated Statistical Measurement of VMIN Degradation," IEEE Transactions on Circuits and Systems-I, Vol. 59, pp. 584-593, Mar. 2012 [Paper]
