2019
Conference
[BioCAS'19] S. Liu, K. Tang, H. Jin, R. Zhang, T. Kim and Y. Zheng, "Continuous wave laser excitation based portable optoacoustic imaging system for melanoma detection," IEEE Biomedical Circuits and Systems Conference, pp. 1-4, Oct. 2019 [Paper]
[ISOCC'19] [Invited] T. Kim, "Overview of Memory Design for Next Generation Applications," 16th International SoC Design Conference, pp. 162-163, Oct. 2019 [Paper]
[ISOCC'19] [Invited] H. Kim, Q. Chen, T. Yoo, T. Kim and B. Kim, “A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks," 16th International SoC Design Conference, pp. 166-167, Oct. 2019 [Paper]
[ISOCC'19] [Invited] J.-Y. Kweon, Y.-H. Song, and T. Kim, “Modelling of Phase Change Memory (PCM) Cell for Circuit Simulation," 16th International SoC Design Conference, pp. 170-171, Oct. 2019 [Paper]
[ESSCIRC'19] [Invited to LSSC] V. L. Le, T. Yoo, J. E. Kim, K.-H. Baek, and T. Kim, “A 213.7-μW Gesture Sensing System-on-Chip with Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65-nm”, IEEE European Solid-State Circuits Conference, pp. 123-126, Sept. 2019 [Paper]
[ESSCIRC'19] H. Kim, Q. Chen, T. Yoo, T. Kim, and B. Kim, “A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation”, IEEE European Solid-State Circuits Conference, pp. 345-348, Sept. 2019 [Paper]
[ISLPED'19] T. Yoo, H. Kim, Q. Chen, T. Kim, and B. Kim, “A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks”, ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 1-6, July 2019 [Paper]
[ISCAS'19] L. Lu, and T. Kim, "A Sequence-Dependent Configurable SRAM PUF for Enhanced Challenge Response Space," IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2019 [Paper]
[EDTM'19] J.-T. Choi, B.-K. An, T. Kim, and Y.-H. Song, "Development of PCM and OTS Macro-models for HSPICE Simulation," 3rd Electron Devices Technology and Manufacturing Conference, pp. 463-465, Mar. 2019 [Paper]
[ICEIC'19] J.-T. Choi, Y.-H. Song, and T. Kim, "Novel Current-mirror Based Time Dependent Sense Scheme for MLC PRAM," International Conference on Electronics, Information, and Communication, pp. 1-3, Jan. 2019 [Paper]
Journal
[ELL'19] J. E. Kim, T. Yoo, K.-H. Baek, and T. Kim, "A balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs," IET Electronics Letters, Vol. 55, Issue 24, pp. 1273-1275 Nov. 2019 [Paper]
[TCAS-I'19] W.-G. Ho, K.-S. Chong, T. Kim, and B.-H. Gwee, "A Secure Data-Toggling SRAM for Confidential Data Protection," IEEE Transactions on Circuits and Systems-I, Vol. 66, pp. 4189-4199, Nov. 2019 [Paper]
[LSSC'19] [Invited] V. L. Le, T. Yoo, J. E. Kim, K.-H. Baek, and T. Kim, “A 213.7-μW Gesture Sensing System-on-Chip with Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65-nm”, IEEE Solid-State Circuits Letters, Vol. 2, pp. 123-126, Sept. 2019 [Paper]
[MEJ'19] A. Garg, Z. C. Lee, L. Lu, and T. Kim, "Improving Uniformity and Reliability of SRAM PUFs Utilizing Device Aging Phenomenon for Unique Identifier Generation," Microelectronics Journal, Elsevier, Vol. 90, pp. 29-38, Aug. 2019 [Paper]
[JSSC'19] Z. C. Lee*, M. S. M. Siddiqui*, Z. H. Kong, and T. Kim, "An 8T SRAM with On-Chip Dynamic Reliability Management and Two-phase Write Operation in 28-nm FDSOI," IEEE Journal of Solid-State Circuits, Vol. 54, pp. 2091-2101, July 2019 (*equally contributed) [Paper]
[MEJ'19] N. Le Ba, S. Oh, D. Sylvester, and T. Kim, "A 256 pixel, 21.6 μW Infrared Gesture Recognition Processor for Smart Devices," Microelectronics Journal, Elsevier, Vol. 86, pp. 49-56, Apr. 2019 [Paper]
[JLPEA'19] M. Jayakrishnan, A. Chang, and T. Kim, "Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience," Journal of Low Power Electronics and Applications, 9, no. 1: 5 [Paper]
[TVLSI'19] A. Do*, S. M. A. Zeinolabedin*, D. Jeon, D. Sylvester, and T. Kim, "An Area Efficient 128-Channel Spike Sorting Processor for Real-time Neural Recording with 0.175 µW per Channel in 65-nm CMOS," IEEE Transactions on VLSI Systems, (*equally contributed), Vol. 27, pp. 126-137, Jan. 2019 [Paper]
