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Learning about Verilog, System Verilog & Other VHDL
This is a Module about learning how to learn and use the hardware language Verilog. I'll be posting my lessons, presentations, labs and other resources. This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.
I'm a huge supporter of Open Source and Creative Commons resources. This is another way of saying Free, Equitable and Accessible resources...
Web Site: WWW.STEAMCLOWN.ORG | Contact: TopClown@STEAMClown.org | LinkedIn: Jim Burnham | TikTok: STEAM Clown
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WORK IN PROGRESS
WORK IN PROGRESS
Construction Zone:
Construction Zone:
Author: Jim Burnham - TopClown@STEAMClown.org. License: Distributed as Open Source.
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. 😅
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. 😅
- Unit: Digital Logic Fundamentals
- Module: Verilog - Technology - Resources
- This is a LEARNING Activity : Lesson / Lab
- Last Revised: June 22, 2025 - Authored: Jan 21, 2024
- Original Author: Jim Burnham - TopClown@STEAMClown.org
- Content License: Distributed as Open Source. See Rights & Usage
Note: TEACHERS!!!! If you are going to use any of these lessons or labs, please let me know. I would really like to understand how you are using this material. I want to know what works, what does not work, what would you like me to add, and how I can make it better. If you changed something, let me know, because it's probably a good idea and you should share it with me, so I can add it and share with everyone else.
This Module or lesson is how I teach in my class. Many of the lessons might be specific to my class, but you could probably adjust them for your class. I'll try to make them a neutral as I can, so they can be used in any Mathematics, Physics, Computer Science, or any other Engineering / Technology class. Let me know how I can make that better. I'll try to keep this unit current and relevant. Please let me know if any resource links are broken or not accessible.
Send me email at TopClown@STEAMClown.org You can also Join the STEAM Clown's Mailing List. If you want to Unsubscribe, click my Unsubscribe From Mailing List link
Overview, Introduction & Prerequisites:
Overview, Introduction & Prerequisites:
Verilog & System Verilog
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a some understanding of basic Math principles.
Prerequisites:
Prerequisites:
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a good understanding of basic computer principles.
Essential Questions:
Essential Questions:
What is a VHDL and Verilog?
Key Academic Vocabulary or Concepts:
Key Academic Vocabulary or Concepts:
Verilog
VHDL
System Verilog
VLSI
Chip Design
Lesson Topic - Verilog & System Verilog:
Lesson Topic - Verilog & System Verilog:
What Do You Already Know? Take This Pre-Quiz To Find Out:
What Do You Already Know? Take This Pre-Quiz To Find Out:
Take the Pre-Quiz to get a better self assessment. Sometimes we feel like we already know a topic, and maybe we can just do a quick review. Other times we find we need to go a little deeper. By taking a quick self assessment, you can measure how much effort you need to put into this section.
Whole Number Pre-Quiz
If you scored 79% or less, you should probably spend a 20-30 min reviewing this section. Even if you scored 100%, it can't hurt to spend 10-15 min.
Do You Need To Build A New Clean Linux Build?
Do You Need To Build A New Clean Linux Build?
If you need to build Linux...
If you need to build Linux...
Check out this short Ubuntu Linux Build Instructions for the Image I use in class.
Here is the Ubuntu Clean Build Shell Script I'm using
wget -O Ubuntu-Clean-Build.sh https://raw.githubusercontent.com/jimTheSTEAMClown/Linux/master/Ubuntu-22-04-2-CleanUpdate.sh
chmod 744 Ubuntu-Clean-Build.sh
./Ubuntu-Clean-Build.sh
Stuff before the Verilog Lessons
Stuff before the Verilog Lessons
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:
These links will be posted later (soon)
Tiny Tapeout - Let's Build A Chip:
Tiny Tapeout - Let's Build A Chip:
Verilog Lessons
Verilog Lessons
High School Learning Verilog Module:
High School Learning Verilog Module:
Introduction and Links
Verilog - Introduction
Verilog - Introduction
In this lesson you will get an overview of Verilog language oal of OpenROAD
Lesson Resources:
Verilog Introduction - 📰 Slide Presentation (Planned Spring 2024)
Verilog Introduction - 📖 Lesson Tutorial - (Planned Spring 2024)
Verilog Introduction - 📽️ 🎧Video - (Planned Fall 2023)
Verilog Introduction - LAB #1 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #2 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #3 - 🛠️ LAB Activity - (Planned Fall 2023)
Mechatronics Engineering Introduction - <topic>
Mechatronics Engineering Introduction - <topic>
This Lesson is coming soon - click here to be notified when it's available - Professional Development Newsletter
Mechatronics - <topic> - 📖 Lesson Tutorial
Mechatronics - <topic> - 📽️ Video / Podcast
Mechatronics - <topic> - 📰 Slide Presentation (Coming Soon)
Mechatronics - <topic> - LAB #1 - 🛠️ LAB Activity
Mechatronics - <topic> - LAB #2 - 🛠️ LAB Activity
Mechatronics - <topic> - LAB #3 - 🛠️ LAB Activity
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