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Learning about Verilog, System Verilog & Other VHDL
This is a Module about learning how to learn and use the hardware language Verilog.Β I'll be posting my lessons, presentations, labs and other resources.Β This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.Β Β
I'm a huge supporter of Open Source and Creative Commons resources.Β This is another way of saying Free, Equitable and Accessible resources...Β Β
Web Site: WWW.STEAMCLOWN.ORG | Contact: TopClown@STEAMClown.org | LinkedIn: Jim Burnham | TikTok: STEAM Clown
Consider Supporting my Open Source STEAM Curriculum Development -- Patrion: Jim The STEAM ClownΒ | Amazon: Amazon Classroom Wishlist, Β
WORK IN PROGRESS
WORK IN PROGRESS
Construction Zone:
Construction Zone:
Author: Jim Burnham -Β TopClown@STEAMClown.org.Β License: Distributed as Open Source.Β
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. π
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. π
- Unit: Digital Logic Fundamentals
- Module: Verilog - Technology - Resources
- This is a LEARNING Activity : Lesson / Lab
- Last Revised: June 22, 2025 - Authored: Jan 21, 2024
- Original Author: Jim Burnham - TopClown@STEAMClown.org
- Content License: Distributed as Open Source. SeeΒ Rights & Usage
Note: TEACHERS!!!! If you are going to use any of these lessons or labs, please let me know.Β I would really like to understand how you are using this material.Β I want to know what works, what does not work, what would you like me to add, and how I can make it better.Β If you changed something, let me know, because it's probably a good idea and you should share it with me, so I can add it and share with everyone else.Β
This Module or lesson is how I teach in my class. Many of the lessons might be specific to my class, but you could probably adjust them for your class.Β I'll try to make them a neutral as I can, so they can be used in any Mathematics, Physics, Computer Science, or any other Engineering / Technology class.Β Let me know how I can make that better. I'll try to keep this unit current and relevant.Β Please let me know if any resource links are broken or not accessible.
Send me email at TopClown@STEAMClown.org Β You can also Join the STEAM Clown's Mailing List.Β If you want to Unsubscribe, click my Unsubscribe From Mailing List link
Overview, Introduction & Prerequisites:
Overview, Introduction & Prerequisites:
Verilog & System Verilog Β
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a some understanding of basic Math principles.
Sponsor Shout Out
Sponsor Shout Out
I would like to thank <Your Company or Organization Here> for their generous support of my classroom and curriculum development.Β <Your Company or Organization Here> has <Your value proposition, call to action, & related content and message>Β
(If you would like to sponsor this, or other Modules or presentation, please contact TopClown@STEAMClown.orgΒ or check out my "How To Help Page"
If you would like to sponsor other Curriculum Development, check out my "How To Help Page" or contactΒ TopClown@STEAMClown.orgΒ
Learning Objective:
Learning Objective:
Module Scope:
- Introduction to Verilog
- Introduction to Silicon layout and Chip design
- Learn Verilog & System VerilogΒ Β
Prior Knowledge:
- No prior knowledge expected - You be you!!!Β
- PC, Laptop or Other device to access the Mathematics web application
- Each lesson will have specific items needed to complete the labs and tasks
Prerequisites:
Prerequisites:
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a good understanding of basic computer principles.
Caution & SafetyΒ Considerations:
Caution & SafetyΒ Considerations:
Primer: Β "Aaron, I can imagine no way in which this thing could be considered anywhere remotely close to safe. All I know is I spent six hours in there and I'm still alive... You still want to do it?"
As with any activity, please make sure you are using appropriate safety equipment. Β If you are coding, writing, reading, or working a lab, make sure you stand up and stretch every hour or so,Β Please consider any safety issues connecting to a Raspberry Pi, Arduino, computers and other electronic equipment.
Essential Questions:
Essential Questions:
What is a VHDL and Verilog?
Key Academic Vocabulary or Concepts:
Key Academic Vocabulary or Concepts:
Verilog
VHDL
System Verilog
VLSI
Chip Design
Lesson Topic - Verilog & System Verilog:
Lesson Topic - Verilog & System Verilog:
What Do You Already Know? Take This Pre-Quiz To Find Out:
What Do You Already Know? Take This Pre-Quiz To Find Out:
Take the Pre-Quiz to get a better self assessment.Β Sometimes we feel like we already know a topic, and maybe we can just do a quick review.Β Other times we find we need to go a little deeper.Β By taking a quick self assessment, you can measure how much effort you need to put into this section.
Whole Number Pre-Quiz
If you scored 79% or less, you should probably spend a 20-30 min reviewing this section. Even if you scored 100%, it can't hurt to spend 10-15 min.
Do You Need To Build A New Clean Linux Build?
Do You Need To Build A New Clean Linux Build?
If you need to build Linux...
If you need to build Linux...
Check out this short Ubuntu Linux Build Instructions for the Image I use in class.
Here is the Ubuntu Clean Build Shell Script I'm using
wget -O Ubuntu-Clean-Build.sh https://raw.githubusercontent.com/jimTheSTEAMClown/Linux/master/Ubuntu-22-04-2-CleanUpdate.sh
chmod 744 Ubuntu-Clean-Build.sh
./Ubuntu-Clean-Build.sh
Stuff before the Verilog Lessons
Stuff before the Verilog Lessons
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:Β
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:Β
These links will be posted later (soon)Β
Verilog - Let's Build A Chip:
Verilog - Let's Build A Chip:
Verilog Lessons
Verilog Lessons
High School Learning Verilog Module:
High School Learning Verilog Module:
Introduction and Links
Digital Logic - VHDL/Verilog Introduction: This is a Module focused on the relationship betweenΒ schematic and text based description.Β it will explore VHDL and Verilog implementations ot some of the logic studied in previous modules.Β
Modules deliverables will include: (about 2 hours of 30 min Lectures & 6+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ
Topics:
Digital Logic - VHDL/Verilog Introduction
VHDL/VerilogΒ Build some of the same logicΒ Schematic circuits using VHDL/Verilog
Verilog - Tools and Project Installation & Build Steps
Verilog - Tools and Project Installation & Build Steps
In this lesson you are going to learn the steps to create your first Open ROAD project.Β You will learn the options to execute the following steps:
Install or upgrade a Linux image on a computer or setup a virtual machine
Run the setup scripts (An automated shell setupOpenROAD.sh will be provided to do most of the heavy lifting)
Setup the Visual Studio Code tools
Validate your install is good and completed without errors
Lesson Resources:
Verilog - Tools and Project Installation - π° Slide Presentation - (Draft for DAC - July 2023)
Verilog - Tools and Project Installation - π Lesson Tutorial - (Planned Fall 2023)
Verilog - Tools and Project Installation - π½οΈ π§Video - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog- Tools and Project Installation - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
π§ 9.2.1 - Digital Logic - RTL (Verilog) 2 GDSII Introduction - π§
π§ 9.2.1 - Digital Logic - RTL (Verilog) 2 GDSII Introduction - π§
Digital Logic - RTL-GDSII Introduction: This Module will cover the generation of RTL and the flow to generate GDSII
Modules deliverables will include: (about 2 hours of 30 min Lectures & 4+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ
Topics:
RTL-GDSII flow Intro
RTL-GDSII simulation and verification flow
Digital Logic - Introduction to the OpenROAD Project: This Module will cover the OpenROAD flows and Scripts
OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. Our project reduces barriers of access and tool costs to democratize system and product innovation in silicon.
The OpenROAD tool and flow provide autonomous, no-human-in-the-loop,
24-hour RTL-GDSII capability to support low-overhead design exploration and implementation through tapeout. We welcome a diverse community of designers, researchers, enthusiasts and entrepreneurs who use and contribute to OpenROAD to make a far-reaching impact.
Links & Resources:
Links that will help us build this project:
Digital Logic - Tiny Tapeout - Logic Gates to Chip Layout: This is a Module about learning how to make a silicon chip and the process that goes into making it. I'll be posting my lessons, presentations, labs and other resources.Β This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ
Topics:
Tools & Wokwi
Student project design
Git Flow
Submit design to verification flows
Final design submission
Silicon Prototype Verification
Reference, Attribution & Resources:
Reference, Attribution & Resources:
License - "Be A Hero"... Distribute Your Content As Open Source... That Is What I'm Doing...
License - "Be A Hero"... Distribute Your Content As Open Source... That Is What I'm Doing...
The content on this site may have been pulled from other open source sites, but typically the interpretation and presentation is primarily the Intellectual Property of Jim Burnham, - TopClown@STEAMClown.org at www.steamclown.org and the Student curriculum can be found under the specific Mechatronics Engineering Units section of this web site.
If you do use my material, and make changes, I would appreciate getting a copy... because if you are making changes, it means that you think there is a better way to teach thisβ¦ and I would really appreciate understanding that. Please send me feedback on my Questions or Feedback form. Please donβt hesitate to ask questions or comment.
You also should keep and include my STEAM Clown Logo and Copyright in any derivative works you create. I would appreciate if you would include one of these images found on my Steam Clown License page and link it to www.steamclown.org
If you do use my material, and make changes, I would appreciate getting a copy... because if you are making changes, it means that you think there is a better way to teach thisβ¦ and I would really appreciate understanding that. Please send me feedback on my Questions or Feedback form. Please donβt hesitate to ask questions or comment.
You also should keep and include my STEAM Clown Logo and Copyright in any derivative works you create. I would appreciate if you would include one of these images found on my Steam Clown License page and link it to www.steamclown.org
Teachers - Unit, Module and Lesson Plans
Teachers - Unit, Module and Lesson Plans
If you are a teacher and want to connect and teach this Lesson or Module, discuss how I teach it, give me feedback, please contact me at TopClown@STEAMClown.orgΒ
To access this Lesson Plan and the Teacher collaboration area, you will have needed to connect with me so I can Share the content with you.Β Please go toΒ the Teachers & Partner Page, check out my Licensing and fill out my Collaboration and Curriculum Request Form.Β I'll review and then grant you access to the requested areas and lesson plans if they exist.
If you have questions or feedback on how I can make a presentation, lesson, lab better please give use my Feedback Form.
Standards Alignments & Objectives:
Standards Alignments & Objectives:
Iβll work on getting these in, but itβs the last thing I want to work on :-) When I have them updated, Iβll move to the top of the Lesson Plan.Β
NGSS: <list standard numbers>
California CTE Standards: <list standard numbers>
Related Instructional Objectives (SWBAT):Β <list standard numbers>
CCSS: nnn, RSIT: nnn, RLST: nnn, WS: nnn, WHSST: nnn, A-CED: nnn, ETS: nnnΒ <list standard numbers>
Main Standard:
Priority standards:
National Standards:
Resource Attribution:
Sites Referenced or Summarized:
Resource Attribution:
Sites Referenced or Summarized:
Reference Text Book - Basic College Mathematics with Early Integers 4th edition - Elayn Martin-Gay - University of New Orleans - Pearson
Reference Sites -Β
Images:
Images:
https://imgbin.com/png/ZJtzkYZZ/under-construction-png
Resource Key:
Resource Key:
<Unit> - <Module Name> - Lessons - Daily/Weekly Lesson Plan
<Unit> - <Module Name> - Lessons - Daily/Weekly Lesson Plan
Key: π° Slides / Audio π§ / π½οΈβΆοΈ Video/YouTube / π§βΆοΈπ½οΈ Audio/Video / β¨ Resources /Β πΌοΈ Tutorial / π Reading Activity / π Writing Activity / π π Reading/Writing / π Coding / π οΈ LAB Activity / π Quiz /Β π Review /Β βοΈ Mastery Check / βοΈ Sign Up /π Extra Credit / πΈοΈ Web Links / π©π½βππ§π½βππ§πΏβππ©βπ« Class / π΅οΈππ Certificate / ποΈ π Collecting Survey Data
/π§ Review / π¦Ύ Practice / πLevel Up /
ποΈπ¦π€π―Β π§
- π¦ Special Project -
Assignment Type: β Establishing (Minimum Standard) / βοΈ Developing (Digging Deeper) / π Aspiring (Putting It Together)
This is an β Establishing Assignment (Minimum Standard)Β - "Everyone Do" Assignment
This is an βοΈ Developing (Digging Deeper) - "Everyone Should Do, To Stretch" Assignment
This is an π Aspiring (Putting It Together)Β - "When you have done the β Establishing andβοΈ Developing" Assignment
π Formative Quiz - π Review
π Quiz -π Mastery Path
π Summative Quiz -βοΈ Skills Mastery Check
Quiz - verify that they are all listed as a "Formative", "Mastery Path", or "Summative"Β
π Formative Quiz - These are quizzes that the students can take a few times. I have them either set for unlimited times, or 3-5 times, where the final score is their average. The idea is that these Formative Quizzes are designed for students to learn and master a skill.Β while I want them to ger 100%, and when it's set to unlimited tries, the student should get 100% eventually.Β When the quiz is set to 3-5 tries with an average, then they should be prepared and should take the quiz seriously. I set the quiz to not show the right answer, but I do let them see their wrong answer.Β I also put the explanation of the right and wrong answer in the right and wrong answer prompt for each question.Β That way they can see why they got the answer wrong and learn from that experience.Β Β
8.1.0.3.2.4 - Python - Ch 3 - Functions - Quiz #2 -Built-In Functions - π Formative Quiz
π Quiz -π Mastery Path - These Mastery path quizzes are to be presented after the student has had a chance to do some labs and some Formative quizzes. Β The goal is to let students have 2 chances to take this quiz, and take the average of the 2 attempts.Β Based on the average, they will be presented with a Canvas Mastery Path, where they will have an option for take additional quiz and assignments to help with remediation.Β This will get them ready to take the Summative Quizzes.
8.1.0.3.3.1 -Β Python - Ch 3 - Functions - Mastery Quiz #1 - π Quiz -π Mastery Path
π Summative Quiz -βοΈ Skills Mastery Check - These Mastery path quizzes are to be presented after the student has had a chance to do some labs and some Formative quizzes. Β The goal is to let students have 2 chances to take this quiz, and take the average of the 2 attempts. That will be their final module/subject topic grade.
8.1.0.3.3.1 -Β Python - Ch 3 - Functions - Skills Mastery Check Quiz #1 - π Summative Quiz -βοΈ Skills Mastery Check
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