Embedded Files
Learning The Verilog,Β Language
This is a Module about learning how to learn and use the hardware language Verilog.Β I'll be posting my lessons, presentations, labs and other resources.Β This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.Β Β
I'm a huge supporter of Open Source and Creative Commons resources.Β This is another way of saying Free, Equitable and Accessible resources...Β Β
Web Site: WWW.STEAMCLOWN.ORG | Contact: TopClown@STEAMClown.org | LinkedIn: Jim Burnham | TikTok: STEAM Clown
Consider Supporting my Open Source STEAM Curriculum Development -- Patrion: Jim The STEAM ClownΒ | Amazon: Amazon Classroom Wishlist, Β
WORK IN PROGRESS
WORK IN PROGRESS
Construction Zone:
Construction Zone:
Author: Jim Burnham -Β TopClown@STEAMClown.org.Β License: Distributed as Open Source.Β
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. π
I'm still working on this Unit... This will be developed in Spring and Spring of 2025 and taught a little in Spring 2024 & 2025, but really for the 2025-2026 school year... I hope... Link to time sheet <-- I forget to track the time, so it's probably 10X these hours. π
- Unit: Digital Logic Fundamentals
- Module: Verilog - Technology - Resources
- This is a LEARNING Activity : Lesson / Lab
- Last Revised: June 22, 2025 - Authored: Jan 21, 2024
- Original Author: Jim Burnham - TopClown@STEAMClown.org
- Content License: Distributed as Open Source. SeeΒ Rights & Usage
Note: TEACHERS!!!! If you are going to use any of these lessons or labs, please let me know.Β I would really like to understand how you are using this material.Β I want to know what works, what does not work, what would you like me to add, and how I can make it better.Β If you changed something, let me know, because it's probably a good idea and you should share it with me, so I can add it and share with everyone else.Β
This Module or lesson is how I teach in my class. Many of the lessons might be specific to my class, but you could probably adjust them for your class.Β I'll try to make them a neutral as I can, so they can be used in any Mathematics, Physics, Computer Science, or any other Engineering / Technology class.Β Let me know how I can make that better. I'll try to keep this unit current and relevant.Β Please let me know if any resource links are broken or not accessible.
Send me email at TopClown@STEAMClown.org Β You can also Join the STEAM Clown's Mailing List.Β If you want to Unsubscribe, click my Unsubscribe From Mailing List link
Overview, Introduction & Prerequisites:
Overview, Introduction & Prerequisites:
Verilog & System Verilog Β
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a some understanding of basic Math principles.
Sponsor Shout Out
Sponsor Shout Out
I would like to thank <Your Company or Organization Here> for their generous support of my classroom and curriculum development.Β <Your Company or Organization Here> has <Your value proposition, call to action, & related content and message>Β
(If you would like to sponsor this, or other Modules or presentation, please contact TopClown@STEAMClown.orgΒ or check out my "How To Help Page"
If you would like to sponsor other Curriculum Development, check out my "How To Help Page" or contactΒ TopClown@STEAMClown.orgΒ
Learning Objective:
Learning Objective:
Module Scope:
- Introduction to Verilog
- Introduction to Silicon layout and Chip design
- Learn Verilog & System VerilogΒ Β
Prior Knowledge:
- No prior knowledge expected - You be you!!!Β
- PC, Laptop or Other device to access the Mathematics web application
- Each lesson will have specific items needed to complete the labs and tasks
Prerequisites:
Prerequisites:
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a good understanding of basic computer principles.
Caution & SafetyΒ Considerations:
Caution & SafetyΒ Considerations:
Primer: Β "Aaron, I can imagine no way in which this thing could be considered anywhere remotely close to safe. All I know is I spent six hours in there and I'm still alive... You still want to do it?"
As with any activity, please make sure you are using appropriate safety equipment. Β If you are coding, writing, reading, or working a lab, make sure you stand up and stretch every hour or so,Β Please consider any safety issues connecting to a Raspberry Pi, Arduino, computers and other electronic equipment.
Essential Questions:
Essential Questions:
What is a VHDL and Verilog?
Key Academic Vocabulary or Concepts:
Key Academic Vocabulary or Concepts:
Verilog
VHDL
System Verilog
VLSI
Chip Design
Lesson Topic - Verilog & System Verilog:
Lesson Topic - Verilog & System Verilog:
What Do You Already Know? Take This Pre-Quiz To Find Out:
What Do You Already Know? Take This Pre-Quiz To Find Out:
Take the Pre-Quiz to get a better self assessment.Β Sometimes we feel like we already know a topic, and maybe we can just do a quick review.Β Other times we find we need to go a little deeper.Β By taking a quick self assessment, you can measure how much effort you need to put into this section.
Whole Number Pre-Quiz
If you scored 79% or less, you should probably spend a 20-30 min reviewing this section. Even if you scored 100%, it can't hurt to spend 10-15 min.
Do You Need To Build A New Clean Linux Build?
Do You Need To Build A New Clean Linux Build?
If you need to build Linux...
If you need to build Linux...
Check out this short Ubuntu Linux Build Instructions for the Image I use in class.
Here is the Ubuntu Clean Build Shell Script I'm using
wget -O Ubuntu-Clean-Build.sh https://raw.githubusercontent.com/jimTheSTEAMClown/Linux/master/Ubuntu-22-04-2-CleanUpdate.sh
chmod 744 Ubuntu-Clean-Build.sh
./Ubuntu-Clean-Build.sh
Stuff before the Verilog Lessons
Stuff before the Verilog Lessons
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:Β
These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems:Β
These links will be posted later (soon)Β
Verilog - Let's Build A Chip:
Verilog - Let's Build A Chip:
Verilog Lessons
Verilog Lessons
High School Learning Verilog Module:
High School Learning Verilog Module:
Introduction and Links
Verilog - Introduction
Verilog - Introduction
In this lesson you will get an overview of Verilog language, learnΒ it's structure, and build some designs in the following Labs
Lesson Resources:
Verilog Introduction - π° Slide Presentation (Planned Spring 2024)
Verilog Introduction - π Lesson Tutorial - (Planned Spring 2024)
Verilog Introduction - π½οΈ π§Video - (Planned Fall 2023)
Verilog Introduction - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Install & Update of the Linux Image - Installation & Build Steps To A Working Linux Image
Verilog - Install & Update of the Linux Image - Installation & Build Steps To A Working Linux Image
In this lesson you are going to install & Update a Ubuntu Linux image.Β We are using the latest version of Ubuntu 24.04.2
Check what version of Ubuntu Linux is installed:Β To check the version of Ubuntu you are running, you can use the lsb_release -a command in the terminal. Alternatively, you can find this information under the "About" section in your system settings (if you're using a desktop version).Β
Here's how to check using the command line:Β
Open the terminal: You can usually find it by searching for "Terminal" in the applications menu or by pressing Ctrl+Alt+T.
Type the command: Enter lsb_release -a and press Enter.
No LSB modules are available.
Distributor ID: Ubuntu
Description: Ubuntu 24.04.2 LTS
Release: 24.04
Codename: noble
Validate your install is good and completed without errors
Links to sort:
gowin Tang-Nano install - https://verilog-meetup.com/wp-content/uploads/2024/10/GOWIN-EDA-Quick-Start-Guide-V6.pdf
Lesson Resources:
Verilog - Tools and Project Installation - π° Slide Presentation - (Draft for DAC - July 2023)
Verilog - Tools and Project Installation - π Lesson Tutorial - (Planned Fall 2023)
Verilog - Tools and Project Installation - π½οΈ π§Video - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog- Tools and Project Installation - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Install of the Gowin Tang-Nano FPGA tools - Installation & Build Steps
Verilog - Install of the Gowin Tang-Nano FPGA tools - Installation & Build Steps
In this π οΈ Lab Activity, you are going to install the Gowan Tang-Nano FPGA tools.Β You will verify that the installation is correct and ready to run the subsequent Verilog Labs.Β
Prerequisite: Install or upgrade a Linux image on a computer or setup a virtual machine (See Previous Linux Installation Lab)
Register and Install Gowan Tang-Nano tools
Run the verification script (An automated shell verifyGowan.sh will verify you have the tools installed.) to validate your install is good and completed without errors
Links to sort or Delete:
gowin Tang-Nano install - https://verilog-meetup.com/wp-content/uploads/2024/10/GOWIN-EDA-Quick-Start-Guide-V6.pdf
Step 1: Register on the Gowan site
Verilog - Gowin Tools and Project Installation - π° Slide Presentation - (TBD)
Go to and Register on the Gowin site - https://www.gowinsemi.com/en/support/download_eda/Β
Step 2: Download The Gowan EDA Tools
Go to and Register on the Gowin site - https://www.gowinsemi.com/en/support/download_eda/Β
Click in the "Software for Linux"
Select the "Gowin_Vxxx Education (Linux x64)
Step 3: Export (TAR) The Gowan EDA Tools
Go to your Downloads directory
cd Downloads
Use the TAR command <-- Update the command to reference the correct version of TAR file you downloaded
tar -xvzf Gowin_V1.9.11.01_Education_Linux.tar.gz
Then you need to move the extracted files to a suitable location, such as a βgowinβ directory inside the user home directory. You can do it using GUI or via command. If the ~/gowin directory already exist, remove or rename it. Then run:
mv ~/Downloads/Gowin_V1.9.11.01_Education_Linux ~/gowin
Verilog - Make Sure VS Code Is Installed
Verilog - Make Sure VS Code Is Installed
Validate your install is good and completed without errors
Lesson Resources:
Verilog - Tools and Project Installation - π° Slide Presentation - (Draft for DAC - July 2023)
Verilog - Tools and Project Installation - π Lesson Tutorial - (Planned Fall 2023)
Verilog - Tools and Project Installation - π½οΈ π§Video - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog- Tools and Project Installation - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Pre-Built - Hackathon Design Examples GitHub - Project Introduction
Verilog - Pre-Built - Hackathon Design Examples GitHub - Project Introduction
In this lesson you are going to make sure you have copied or cloned the Verilog Hackathon design examples.
Directory locations for pre-built source files
Running the Bash flow
Validating your design process correctly
Lesson Resources:
Verilog - Pre-Built Project Introduction Exploration - π° Slide Presentation - (Draft for DAC - July 2023)
Verilog - Pre-Built Project Introduction Exploration - π Lesson Tutorial - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - π½οΈ π§Video - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Your First Verilog Project - Building A Verilog Counter Design
Verilog - Your First Verilog Project - Building A Verilog Counter Design
In this lesson you are going to explore the creation of your first Verilog OpenROAD Project.Β You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:
Directory locations for Verilog source files
Directory, Module and File naming conventions
Config andΒ Constraint parameters and settings
Running the make flow
Validating your design process correctly
Lesson Resources:
Verilog - Building A New Verilog Counter Design - π° Slide Presentation - (Draft for DAC - July 2023)
Verilog - Building A New Verilog Counter Design - π Lesson Tutorial - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - π½οΈ π§Video - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #1 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #2 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #3 - π οΈ LAB Activity - (Planned Fall 2023)
Verilog - Virtual Studio Code - Project Introduction
Verilog - Virtual Studio Code - Project Introduction
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - π° Slide Presentation (Coming Soon - Placeholder Link)
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - π Lesson Tutorial
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - π½οΈ π§Video
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #1 - π οΈ LAB Activity
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #2 - π οΈ LAB Activity
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #3 - π οΈ LAB Activity
Verilog - Verilog Synthesis
Verilog - Verilog Synthesis
Verilog - Verilog Synthesis Flow - π° Slide Presentation (Coming Soon - Placeholder Link)
Verilog - Verilog Synthesis Flow - π Lesson Tutorial
Verilog - Verilog Synthesis Flow - π½οΈ π§Video
Verilog - Verilog Synthesis Flow - LAB #1 - π οΈ LAB Activity
Verilog - Verilog Synthesis Flow - LAB #2 - π οΈ LAB Activity
Verilog - Verilog Synthesis Flow - LAB #3 - π οΈ LAB Activity
Lecture and Lab Topics:
The-OpenROAD-Project Intro
OpenROAD RTL-GDSII simulation and verification flow
Building blocks of open-source design (this should introduce .libs. .v source and public pdks briefly if not covered in the previous module covering RTL-GDSII)
Running the OpenROAD flow from RTL-GDSII (key stages and intermediate results briefly)
Key advantages and features of OpenROAD flow
OpenROAD GUI Introduction
Validating the design for Tapeout - My First Chip Labs - 4-5 labs that incorporate the following steps, to complete a design ready for submission
Lab #1 - Initial tools and flow for placement setup
Initialize floorplan - define the chip size and cell rows
Place pins (for designs without pads )
Lab #2 - Using Macros and other Structures
Place macro cells (RAMs, embedded macros)
Insert substrate tap cells
Insert power distribution network
Macro Placement of macro cells
Global placement of standard cells
Lab #3 - Checking and Adjusting Timing and Placement
Repair max slew, max capacitance, and max fanout violations and long wires
Clock tree synthesis
Optimize setup/hold timing
Lab #4 - Finishing Touches
Insert fill cells
Global routing (route guides for detailed routing)
Antenna repair
Detailed routing
Parasitic extraction
Lab #5 - Final Analysis
Static timing analysis
Contributing to the open-source design community using the OpenROAD ecosystem
Each lecture and lab modules will contain the following collateral and curriculum so that a STEAM teacher anywhere in a Highschool or Community College can implement the course work.Β
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ
Working Topics - Move or Delete
Working Topics - Move or Delete
links:
links:
https://science.xyz/news/launching-science-foundryΒ - work on getting high school flow.
Logic Gates Introduction - <topic>
Logic Gates Introduction - <topic>
Here is the outline I was thinking of: 3 hr lecture- 3 hr labs
1. Define what is meant by RTL 2 GDSII in general for ASIC applications.
A lecture to show the basics of a typical ASIC Design flow. You can explain this in the context of OpenROAD as well.
Also introduce the building blocks such as libraries, PDKS, rules, constraints etc briefly.
I have attached a set of slides based on our current presentation--this may be too complex but it gives you an idea of the flow. The design images can be substituted by a simpler example like GCD. (Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd)
2. Show the RTL- GDS flow in OpenROAD-flow-scripts
Explain briefly input/outputs at each stage and handoffs of the flow and the associated functional role.
e.g a Systems architect - designs the system given the components with a targeted design goal for power, performance, area
RTL engineer- Defines the register transfer level based on the architecture and synthesizes a netlist (Verilog, VHDL etc.) . We support Verilog.
3. Introduction to physical design - basic concepts of standard cell placement , creation of a power grid, i/o pins to connect to the external world,
goals - reducing wirelength
4. Some basic analysis like timing, area utilization, density etc. using the OpenROAD GUI.
5. Final chip handoff- importance of ensuring that this design can be made manufacturable based on skywater 130nm or GF180 pdk.
Lab demo - GCD (greatest common divisor) from ORFS Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd
I can help set you up with ORFS and share a simple demoΒ example.
Student project- Pick any design from the ORFS design repo, choose a design goal and improve that (area, utiization, timing etc)
Extra credit- Student selects any open source design core and completes the flow in ORFS.
- Submit a GitHub issue (problem found) or a fixΒ via a PR from the ORFS set of issues to contribute. This may be a huge stretch goal but students inclined towards software, scripts, document improvements can contribute.
Here's a MEMS foundry that was recently launched recently--something that could be very useful for your class.
https://science.xyz/news/launching-science-foundry
Here's the latest infor on Tiny Tapeout: https://www.youtube.com/watch?v=fblSVCPvCiYΒ
We should include a plan for student projects on Tiny Tapeout.
NSF Link to teacher Education research grant opportunities
OpenROAD Introduction
OpenROAD Introduction
Digital Logic - Introduction to the OpenROAD Project: This Module will cover the OpenROAD flows and Scripts
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)Β
Google Docs: π° Slide Presentation / πΌοΈ Lesson Tutorial / β¨ Resources
Canvas LMS Module: π οΈ LAB Activities and π Formative & Summative AssessmentsΒ
Notes: This is a comment from @dralabeing that I need to follow up on, where to add some more timing analysis: Timing analysis is generally done at different stages- first time pre-layout after CTS, post-global-routing, after detailed routing and chip finishing. So this topic can be introduce sooner.Β
Links & Resources:
Topics:
The-OpenROAD-Project Intro
OpenROAD RTL-GDSII simulation and verification flow
Building blocks of open-source design (this should introduce .libs. .v source and public pdks briefly if not covered in the previous module covering RTL-GDSII)
Running the OpenROAD flow from RTL-GDSII (key stages and intermediate results briefly)
Key advantages and features of OpenROAD flow
OpenROAD GUI Introduction
Validating the design for Tapeout - My First Chip Labs - 4-5 labs that incorporate the following steps, to complete a design ready for submission
Lab #1 - Initial tools and flow for placement setup
Initialize floorplan - define the chip size and cell rows
Place pins (for designs without pads )
Lab #2 - Using Macros and other Structures
Place macro cells (RAMs, embedded macros)
Insert substrate tap cells
Insert power distribution network
Macro Placement of macro cells
Global placement of standard cells
Lab #3 - Checking and Adjusting Timing and Placement
Repair max slew, max capacitance, and max fanout violations and long wires
Clock tree synthesis
Optimize setup/hold timing
Lab #4 - Finishing Touches
Insert fill cells
Global routing (route guides for detailed routing)
Antenna repair
Detailed routing
Parasitic extraction
Lab #5 - Final Analysis
Static timing analysis
Contributing to the open-source design community using the OpenROAD ecosystem
Links that will help us build this project:
Logic Gates Introduction - <topic>
Logic Gates Introduction - <topic>
This Lesson is coming soon - click here to be notified when it's available - Professional Development Newsletter
Mechatronics - <topic> - π Lesson Tutorial
Mechatronics - <topic> - π½οΈ Video / π§Β Podcast
Mechatronics - <topic> - π° Slide Presentation (Coming Soon)
Mechatronics - <topic> - LAB #1 - π οΈ LAB Activity
Mechatronics - <topic> - LAB #2 - π οΈ LAB Activity
Mechatronics - <topic> - LAB #3 - π οΈ LAB Activity
Mechatronics Engineering Introduction - <topic>
Mechatronics Engineering Introduction - <topic>
This Lesson is coming soon - click here to be notified when it's available - Professional Development Newsletter
Mechatronics - <topic> - π Lesson Tutorial
Mechatronics - <topic> - π½οΈ Video / Podcast
Mechatronics - <topic> - π° Slide Presentation (Coming Soon)
Mechatronics - <topic> - LAB #1 - π οΈ LAB Activity
Mechatronics - <topic> - LAB #2 - π οΈ LAB Activity
Mechatronics - <topic> - LAB #3 - π οΈ LAB Activity
Reference, Attribution & Resources:
Reference, Attribution & Resources:
License - "Be A Hero"... Distribute Your Content As Open Source... That Is What I'm Doing...
License - "Be A Hero"... Distribute Your Content As Open Source... That Is What I'm Doing...
The content on this site may have been pulled from other open source sites, but typically the interpretation and presentation is primarily the Intellectual Property of Jim Burnham, - TopClown@STEAMClown.org at www.steamclown.org and the Student curriculum can be found under the specific Mechatronics Engineering Units section of this web site.
If you do use my material, and make changes, I would appreciate getting a copy... because if you are making changes, it means that you think there is a better way to teach thisβ¦ and I would really appreciate understanding that. Please send me feedback on my Questions or Feedback form. Please donβt hesitate to ask questions or comment.
You also should keep and include my STEAM Clown Logo and Copyright in any derivative works you create. I would appreciate if you would include one of these images found on my Steam Clown License page and link it to www.steamclown.org
If you do use my material, and make changes, I would appreciate getting a copy... because if you are making changes, it means that you think there is a better way to teach thisβ¦ and I would really appreciate understanding that. Please send me feedback on my Questions or Feedback form. Please donβt hesitate to ask questions or comment.
You also should keep and include my STEAM Clown Logo and Copyright in any derivative works you create. I would appreciate if you would include one of these images found on my Steam Clown License page and link it to www.steamclown.org
Teachers - Unit, Module and Lesson Plans
Teachers - Unit, Module and Lesson Plans
If you are a teacher and want to connect and teach this Lesson or Module, discuss how I teach it, give me feedback, please contact me at TopClown@STEAMClown.orgΒ
To access this Lesson Plan and the Teacher collaboration area, you will have needed to connect with me so I can Share the content with you.Β Please go toΒ the Teachers & Partner Page, check out my Licensing and fill out my Collaboration and Curriculum Request Form.Β I'll review and then grant you access to the requested areas and lesson plans if they exist.
If you have questions or feedback on how I can make a presentation, lesson, lab better please give use my Feedback Form.
Standards Alignments & Objectives:
Standards Alignments & Objectives:
Iβll work on getting these in, but itβs the last thing I want to work on :-) When I have them updated, Iβll move to the top of the Lesson Plan.Β
NGSS: <list standard numbers>
California CTE Standards: <list standard numbers>
Related Instructional Objectives (SWBAT):Β <list standard numbers>
CCSS: nnn, RSIT: nnn, RLST: nnn, WS: nnn, WHSST: nnn, A-CED: nnn, ETS: nnnΒ <list standard numbers>
Main Standard:
Priority standards:
National Standards:
Resource Attribution:
Sites Referenced or Summarized:
Resource Attribution:
Sites Referenced or Summarized:
Reference Text Book - Basic College Mathematics with Early Integers 4th edition - Elayn Martin-Gay - University of New Orleans - Pearson
Reference Sites -Β
Images:
Images:
https://imgbin.com/png/ZJtzkYZZ/under-construction-png
New ToC
New ToC
Section 0: Getting Started
Section 0: Getting Started
0.1 Introduction to Digital Design and Verilog
0.2 ASIC vs FPGA: Whatβs the Difference?
0.3 Verilog Design Flow Overview (Simulation, Synthesis, Implementation)
Section 1: Hardware & Software Setup
Section 1: Hardware & Software Setup
FPGA Toolchains
Installing and Running a Verilog Project
Connecting Hardware
Your First Verilog "Hello World" (LED Blink Example)
Section 2: Verilog Language Basics
Section 2: Verilog Language Basics
1.1 Module Structure and Syntax
1.2 Ports and Port Directions
1.3 Data Types and Net vs. Reg
1.4 Operators (Arithmetic, Logical, Bitwise, Reduction)
1.5 Continuous Assignments and assign
1.6 Initial and Always Blocks
1.7 Blocking vs Non-Blocking Assignments
Possible Topics
Possible Topics
π Verilog HDL Tutorial Table of Contents
π Verilog HDL Tutorial Table of Contents
Beginner Level β Targeting FPGA and ASIC Design
Beginner Level β Targeting FPGA and ASIC Design
Section 0: Getting Started
Section 0: Getting Started
0.1 Introduction to Digital Design and Verilog
0.2 ASIC vs FPGA: Whatβs the Difference?
0.3 Verilog Design Flow Overview (Simulation, Synthesis, Implementation)
0.4 Required Tools and Setup
0.4.1 Verilog Simulators (ModelSim, Icarus Verilog)
0.4.2 FPGA Toolchains (Intel Quartus, Xilinx Vivado)
0.4.3 ASIC Tool Overview (e.g., Synopsys Design Compiler)
0.4.4 Installing and Running a Verilog Project
0.5 Your First Verilog "Hello World" (LED Blink Example)
Section 1: Verilog Language Basics
Section 1: Verilog Language Basics
1.1 Module Structure and Syntax
1.2 Ports and Port Directions
1.3 Data Types and Net vs. Reg
1.4 Operators (Arithmetic, Logical, Bitwise, Reduction)
1.5 Continuous Assignments and assign
1.6 Initial and Always Blocks
1.7 Blocking vs Non-Blocking Assignments
Section 2: Combinational Logic Design
Section 2: Combinational Logic Design
2.1 Gates, Adders, and Multiplexers
2.2 Case Statements and If-Else
2.3 Designing a 4-to-1 Multiplexer
2.4 Combinational ALU (Arithmetic Logic Unit)
2.5 Best Practices for Synthesizable Combinational Code
Section 3: Sequential Logic Design
Section 3: Sequential Logic Design
3.1 Flip-Flops and Latches
3.2 Edge Sensitivity and Clocking
3.3 Counters and Shift Registers
3.4 FSM Design (Finite State Machines)
3.5 Synchronous Reset vs Asynchronous Reset
3.6 Best Practices for Sequential Logic
Section 4: Structural and Hierarchical Design
Section 4: Structural and Hierarchical Design
4.1 Instantiating Modules
4.2 Parameterized Modules
4.3 Generating Hardware with generate and for
4.4 Designing a Simple 4-bit CPU (Modular Hierarchy)
Section 5: Simulation and Testbenches
Section 5: Simulation and Testbenches
5.1 Writing a Simple Testbench
5.2 $display, $monitor, and $dumpvars
5.3 Behavioral vs Synthesizable Code
5.4 Using Waveform Viewers
5.5 Verilog Assertions (Intro)
Section 6: FPGA and ASIC Implementation Workflow
Section 6: FPGA and ASIC Implementation Workflow
6.1 Synthesizing Your Design (FPGA)
6.2 FPGA Constraints and Pin Assignment
6.3 Uploading to an FPGA (e.g., Blinking an LED)
6.4 Timing Constraints and Static Timing Analysis
6.5 Brief Introduction to ASIC Flow and Tools
6.6 Gate-Level Netlist and Post-Synthesis Simulation
Section 7: Common Digital Design Projects
Section 7: Common Digital Design Projects
7.1 7-Segment Display Controller
7.2 UART Transmitter/Receiver
7.3 PWM Generator
7.4 Stopwatch with Display
7.5 Memory-Mapped I/O Design
Appendices
Appendices
A. Verilog Reserved Keywords
B. Common Verilog Coding Pitfalls
C. Glossary of Digital Design Terms
D. Tool Setup Tutorials (Linux/Windows/Mac)
E. FPGA Board-Specific Notes (e.g., DE10-Lite, Basys3)
Resource Key:
Resource Key:
<Unit> - <Module Name> - Lessons - Daily/Weekly Lesson Plan
<Unit> - <Module Name> - Lessons - Daily/Weekly Lesson Plan
Key: π° Slides / Audio π§ / π½οΈβΆοΈ Video/YouTube / π§βΆοΈπ½οΈ Audio/Video / β¨ Resources /Β πΌοΈ Tutorial / π Reading Activity / π Writing Activity / π π Reading/Writing / π Coding / π οΈ LAB Activity / π Quiz /Β π Review /Β βοΈ Mastery Check / βοΈ Sign Up /π Extra Credit / πΈοΈ Web Links / π©π½βππ§π½βππ§πΏβππ©βπ« Class / π΅οΈππ Certificate / ποΈ π Collecting Survey Data
/π§ Review / π¦Ύ Practice / πLevel Up /
ποΈπ¦π€π―Β π§
- π¦ Special Project -
Assignment Type: β Establishing (Minimum Standard) / βοΈ Developing (Digging Deeper) / π Aspiring (Putting It Together)
This is an β Establishing Assignment (Minimum Standard)Β - "Everyone Do" Assignment
This is an βοΈ Developing (Digging Deeper) - "Everyone Should Do, To Stretch" Assignment
This is an π Aspiring (Putting It Together)Β - "When you have done the β Establishing andβοΈ Developing" Assignment
π Formative Quiz - π Review
π Quiz -π Mastery Path
π Summative Quiz -βοΈ Skills Mastery Check
Quiz - verify that they are all listed as a "Formative", "Mastery Path", or "Summative"Β
π Formative Quiz - These are quizzes that the students can take a few times. I have them either set for unlimited times, or 3-5 times, where the final score is their average. The idea is that these Formative Quizzes are designed for students to learn and master a skill.Β while I want them to ger 100%, and when it's set to unlimited tries, the student should get 100% eventually.Β When the quiz is set to 3-5 tries with an average, then they should be prepared and should take the quiz seriously. I set the quiz to not show the right answer, but I do let them see their wrong answer.Β I also put the explanation of the right and wrong answer in the right and wrong answer prompt for each question.Β That way they can see why they got the answer wrong and learn from that experience.Β Β
8.1.0.3.2.4 - Python - Ch 3 - Functions - Quiz #2 -Built-In Functions - π Formative Quiz
π Quiz -π Mastery Path - These Mastery path quizzes are to be presented after the student has had a chance to do some labs and some Formative quizzes. Β The goal is to let students have 2 chances to take this quiz, and take the average of the 2 attempts.Β Based on the average, they will be presented with a Canvas Mastery Path, where they will have an option for take additional quiz and assignments to help with remediation.Β This will get them ready to take the Summative Quizzes.
8.1.0.3.3.1 -Β Python - Ch 3 - Functions - Mastery Quiz #1 - π Quiz -π Mastery Path
π Summative Quiz -βοΈ Skills Mastery Check - These Mastery path quizzes are to be presented after the student has had a chance to do some labs and some Formative quizzes. Β The goal is to let students have 2 chances to take this quiz, and take the average of the 2 attempts. That will be their final module/subject topic grade.
8.1.0.3.3.1 -Β Python - Ch 3 - Functions - Skills Mastery Check Quiz #1 - π Summative Quiz -βοΈ Skills Mastery Check
Page updated
Google Sites
Report abuse