- For CNTFET, Gate capacitance significantly increases with the use of high κ.
- For CNTFET, Gate capacitance increases to a small amount with oxide thickness.
- For SBCNTFET, Current and gm are significantly increases for high κ dielectric. For low κ (=3.9) dielectric SiO2, SS is 125 mV/dec, where for HfO2 (κ=16) and ZrO2 (κ=25) SS is much lower.
- For SBCNTFET, slightly higher ON current and transconductance is found for thinner gate dielectric.
- Drain current exhibits insignificant change with temperature.
- Transconductance profile also shows negligible change for above 0.2V gate bias and decreases
- with temperature for sub-0V condition. On the other hand, SS is significantly decreased for lower temperature.
- Equally doped S/D and channel with no potential gradient shows greater On/off ratio and lower SS. On current increases slightly and Off current decreases remarkably for long gate. S/D length has no effect in On current, but Off current is lower for short S/D. Though On current increases with CNT diameter, Off current increases more drastically to reduce On/off ratio and degrade SS.
(13, 0) zigzag CNT channel with 10-20nm length is found optimum to be used in channel.
The simulator can be found in my github page in this link: https://github.com/mdshafayat/CNT-MOSFET