The title of my undergraduate dissertation is, Multidimensional Modeling and Characterization of Electrostatics and Transport of Gate-All-Around InxGa1-xAsNanowire MOSFET and Beyond for Ultra High Performance Application

Abstract:

The era of planar bulk MOSFETs are over and Intel has moved on to 3D Nano-scale devices, 22 nm Si trigate FinFETs are being used in present microprocessors. To suppress the short channel effects of Nano-scale devices III-V materials have become topic of extensive research. To scale down to 10 nm feature size, SCE effects must be dealt with. Among all the Multi-gate devices, Gate-all-around architecture on Si CMOS has been proven most resistant to SCE. Gate-all-around In_xGa_1-xAs nanowire MOSFET with ALD Al₂O₃ as gate dielectric has been experimentally demonstrated by JJ Gu et al. We developed a 2-D FEM based numerical model to characterize the Gate-all-around MOSFET self-consistently. Finite element method has been used to solve Poisson’s equation and Schrödinger’s equation self-consistently, considering wave function penetration and other quantum effects. COMSOL Multiphysics is used as the PDE solver tool which is invoked from MATLAB by using the scripting language of COMSOL. The self-consistent model is verified with ATLAS simulations. We evaluate here the Full C-V characteristics considering both accumulation and inversion region which is essential for device modeling and high frequency performance evaluation which have not been reported yet experimentally. C-V characteristics is also calculated semi-classically only solving Poisson’s equation iteratively and the result divulge the necessity of incorporating quantum effects in the modeled device. Variation in C-V characteristics due to its functional dependence on fin-width, oxide thickness, doping density are also studied. We also present an analytic model for calculating potential profile and threshold voltage of the same device incorporating quantum mechanical corrections. An empirical formula is also developed to derive gate capacitance in both accumulation and inversion region. The analytical model is also verified with ATLAS simulations. To study the transport characteristics, firstly we extend the two energy level system model by S. Dattta to N-energy level system for our device and then Non-equilibrium Green’s function based transport model is applied incorporating inelastic scattering taking the source Fermi-level from the 2-D simulator. This approach gives an underestimate of the device current. Landauer approach assuming transmission coefficient as a step function is also adopted for calculating current in ballistic regime taking DIBL effect into account. A 3-D simulator is developed for achieving a better estimate of the current. We adopt mode space approach solving Poisson’s equation in 3-D and Schrödinger’s equation in 2-D for different cross-sections to obtain Eigen energy and coupling them to form 3-D carrier concentration profiles. Then using Landauer approach ballistic current is calculated for the device in 3-D. Then the ON current, sub-threshold swing, Quantum capacitance, transconductance, delay products are calculated to analyze device performance. We suggest a new Gate-all-around device structure changing the channel to an axially composition-graded nanowire channel with possibility to apply graded doping. Bi-axial compressive strain is introduced in composition-graded nanowire channel. The effect of strain on bandgap and effective mass is calculated using Luttinger formulae. C-V characterization of this device is performed with 2-D numerical model and ballistic current is calculated from Landauer approach. Then the performance of this device is compared with the simple GAA device. This new device has better interface characteristics i.e. lower interface traps, greater transconductance, lower gate-leakage current and possibility to tune threshold voltage by introducing graded-doping. Our work provides insightful observation towards designing the GAAFET with best possible performance which should be the immediate next generation transistors after Trigate FinFET which is commercially available. Fabrication technology is adapted for Multi-gate 3-D transistors, so it is only a matter of time to industrialize the studied device to achieve the target scaling and performance predicted by ITRS road map. Our work also suggests a novel structure with enhanced performance which can be useful in mitigating interface trap defects as well as reducing leakage rendering the possibility of further scaling.