• Developed physically based 2D and 3D self-consistent simulator with MATLAB and COMSOL Multiphysics to examine electrostatics and transport characteristics of III-V Nanowire Gate-all-around MOSFET. The simulator can be found in my github page in this link: https://github.com/mdshafayat/III-V-nanowire-GAAFET
• Developed a modified algorithm to extract Dit profile
• Computed gate leakage current using Schuegraf-Hu formula
• Computed ballistic current and quasi-ballistic current
• Proposed analytic formulas for threshold voltage, charge calculation, gate capacitance and drain current and they are generalized for MuGFETs
• Proposed semi-empirical compact formula for Transmission co-efficient to calculate current without incorporating Buttiker probe in Mode space approach

• GAA device has a sharp transition in threshold voltage at lower fin width due to volume inversion.
• Higher current is achieved for lower oxide thickness and about 20nm fin width with In_0.75Ga_0.25As. For In_0.53Ga_0.47As, 30nm fin width device; gate leakage is almost 4% of ballistic current for 1.5nm oxide thickness. For above 2nm oxide thickness, gate leakage is almost negligible. So, the III-V Nanowire GAAFET with ALD Al₂O₃ as Gate Dielectric is well-resistant to gate leakage.
• For lower fin-width, the device shows greater ON/OFF ratio and smaller delay-products.
• Lower Sub-threshold swing is observed for lower doping density

Key Publication:

• Saeed Uz Zaman Khan, Md. Shafayat Hossain, Fahim Ur Rahman, Rifat Zaman, Md. Obaidul Hossen, Quazi D. M. Khosru, Impact of high-κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate-all-around nanowire transistor, International Journal of Numerical Modeling: Electronic Networks, Devices and Fields 28, 389-403, (2014).

Abstract: High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1-xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m^-3, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m^-3, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ).

[Article] [pdf]

Other Publications:

International Journals:

1. Quazi D. M. Khosru, Saeed Uz Zaman Khan, Md. Shafayat Hossain, Md. Obaidul Hossen, Fahim Ur Rahman, Rifat Zaman, “Capacitance-Voltage Characteristics of Gate-All-Around InxGa1-xAs Nanowire Transistor”, ECS Transaction, vol. 53, issue 1, p. 169-176, 2013. ( Presented in 223rd ECS Meeting, Toronto, Canada, May 2013) [pdf]

International Conferences:

1. Saeed Uz Zaman Khan, Md. Shafayat Hossain, Md Obaidul Hossen, Fahim Ur Rahman, Rifat Zaman, Quazi DM Khosru, Analytical modeling of gate capacitance and drain current of gate-all-around InxGa1− xAs nanowire MOSFET, 2nd International Conference on Electronic Design (ICED), 2014, Penang, Malaysia. [pdf]
2. Saeed Uz Zaman Khan, Md. Shafayat Hossain, Fahim Ur Rahman, Rifat Zaman, Md. Obaidul Hossen, Quazi D. M. Khosru, Uncoupled mode space approach towards transport modeling of Gate-All-Around InxGa1−xAs nanowire MOSFET, International Conference on Electrical and Computer Engineering (ICECE), 2014, Dhaka, Bangladesh. [pdf]
3. Md. Shafayat Hossain, Saeed Uz Zaman Khan, Md. Obaidul Hossen, Fahim Ur Rahman, Rifat Zaman, Quazi D. M. Khosru, “Analytical Modeling of Potential Profile and Threshold Voltage forRectangular Gate-all-around III-V Nanowire MOSFETs with ATLAS Verification”, IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Bangkok, Thailand, Dec. 3-5, 2012. [pdf]
4. Md. Obaidul Hossen, Md. Shafayat Hossain, Saeed Uz Zaman Khan, Fahim Ur Rahman, Rifat Zaman, Quazi D. M. Khosru, “Ballistic Performance limit and Gate Leakage Modeling of Rectangular Gate-all-around InGaAs Nanowire Transistors with ALD Al2O3 as Gate Dielectric”, IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Bangkok, Thailand, Dec. 3-5, 2012. [pdf]
5. Fahim Ur Rahman, Md. Shafayat Hossain, Saeed Uz Zaman Khan, Md. Obaidul Hossen, Rifat Zaman, Quazi D. M. Khosru, “Characterization of Interface Trap Density of In-rich InGaAs Gate-all-around Nanowire MOSFETs”, in PROC. International Conference on Electrical and Computer Engineering, Dhaka, Bangladesh, pp. 674-677, Dec. 2012. [pdf]
6. Rifat Zaman, Saeed Uz Zaman Khan, Md. Shafayat Hossain, Md. Obaidul Hossen, Fahim Ur Rahman, Quazi D. M. Khosru, “Self-Consistent Determination of Threshold Voltage of In-rich Gate-all-around InxGa1-xAs Nanowire Transistor Incorporating Quantum Mechanical Effect”, in PROC. International Conference on Electrical and Computer Engineering, Dhaka, Bangladesh, pp. 678-681, Dec. 2012. [pdf]
7. Saeed Uz Zaman Khan, Md. Shafayat Hossain, Fahim Ur Rahman, Md Obaidul Hossen, Rifat Zaman, Quazi DM Khosru, “Carrier Transport Phenomena in Cylindrical Channel III-V Gate-All-Around Nanowire Transistor”, International Semiconductor Device Research Symposium 2013, Maryland, USA. [pdf]