VHDL Serial Divider

Divide and conquer, one bit at a time 

My Python version of my VHDL divider, try it out! Dividend and divisor should be inputed as decimal numbers.

It may be written in Python, but it still does the same finite state machine and bit operations I do in my VHDL version. (I've made a habit of implementing digital algorithms in Python first because Python is a "bit" easier to debug :)).  Look at the verbose output to see how I'm implementing the algorithm.