High Bandwidth TIA
High Bandwidth TIA
From small currents to big gains
From small currents to big gains
Embedded Files
Class Name: EE/MedE 114b (Advanced Analog Design)
Institution: Caltech (Undergrad)
Project Duration: May 2025
Project Description: Design a low-power differential TIA with transconductance 5 kOhms over 5 GHz, among other specifications
Project Work
Project Work
EE 114b Final Project.pptx.pdfProject presentation
Cadence files here
Ruth Berkun -- EE 114b Final Project Report.pdfProject report
What I learned
What I learned
Skills Exercised/Gained
Skills Exercised/Gained
Cadence schematic design & transistor-level simulation in 65 nm CMOS
Pole-zero placement (including complex poles)
Gain–bandwidth optimization under feedback and parasitic effects
Differential signaling implementation for noise and performance gains
Hand estimation and small-signal analysis to predict and verify DC gain, bandwidth, and noise
Noise modeling & input-referred noise extraction in the GHz range
Design tradeoff evaluation for power, linearity, and headroom
Post Mortem
Post Mortem
The original course specification (which I misunderstood) defined gain as the output voltage divided by the input current before the input coupling network.
My simulations measured gain as the output voltage divided by the input current into the TIA stage itself. Under this stage-referenced definition, the design achieved a gain of 5000 V/A with a −3 dB bandwidth of 5.3 GHz.
When referred to the front-end input current per the original spec, the design falls short of the required gain due to attenuation in the capacitive input network.
Opportunities for improvement:
Adjust DC biasing of gain stage and/or buffers to restore output centering and maximize headroom
Or, buffer that is not a source follower (CMOS push-pull, for example)
Cascode transistors on gain stage to maintain VDS margin and improve linearity
Implement a second gain stage after the TIA to recover the required gain while maintaining bandwidth
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