SH-2 CPU
SH-2 CPU
Full of RISCy pipeline moves
Full of RISCy pipeline moves
Embedded Files
Class Name: EE 188 (CPU Architecture)
Institution: Caltech (Undergrad)
Project Duration: June 2025
Project Description: Cycle-accurate VHDL simulation of the Hitachi SH-2 RISC CPU
Joint project with Nerissa Finnen
Project Work
Project Work
All our VHDL code, testbenches, and instructions on how to use it to run your own programs
What I learned
What I learned
Skills Exercised/Gained
Skills Exercised/Gained
GHDL and GTKWave
VHDL programming and testbenching
VHDL interaction with external text files
Finite state machines
Introducing pipeline stalls and counteracting pipeline hazards
Memory accesses
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