Basic CPU
Basic CPU
Embedded Files
Class Name: EE/CS 10a (Introduction to Digital Logic and Embedded Systems)
Institution: Caltech (Undergrad)
Project Duration: January-March 2023
Project Description: Design and simulate a simple CPU out of logic gates
My Work
My Work
Full CPU here, in ABEL hardware description language.
caltech10.pdfCPU overal structure and functionality. Courtesy Prof. Glen George
ALU.pdfALU Unit design: Performs addition, subtraction, shift, and logical operations
Dmau.pdfDMAU: Generates data addresses, responsible for updating X and S registers
pmau.pdfPMAU: Generates program memory addresses, updates program counter (PC)
Control+unit.pdfControl Unit: Interprits instruction register to generate control signals for ALU, PMAU, and DMAU. Also generates RD and WR signals. This PDF only details how the CPU handles single clock instructions.
final cpu.pdfControl Unit finite state machine (For dealing with CALL and RTS instructions, which take multiple clocks)
What I learned
What I learned
Skills Exercised/Gained
Skills Exercised/Gained
ABEL programming language
Finite state machines
Karnaugh maps
CPU system architecture
Page updated
Google Sites
Report abuse