Delay-Locked Loop
Delay-Locked Loop
DLL: Delay, Lock, Lament
DLL: Delay, Lock, Lament
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Class Name: EE/MedE 124 (Mixed-Mode ICs)
Institution: Caltech (Undergrad)
Project Duration: March 2025
Project Description: A DLL that locks to 8 GHz at 3 different phase offsets, among other specs
Joint project with Nerissa Finnen
Project Work
Project Work
EE 124 Final Report.pdfIEEE-style report.
Of course, IEEE writers never give you actual reproducable schematics, so I've provided reproducable schematics on the right, with numbers for the transistor lengths and widths.
Overall schematic. Everything above the blocks simulates the input and output sin waves with varying levels of noise.
Inverter width: 1u, buffer width: 0.121u, all transistors 45 nm, beta = 1.66
Phase detector: WPd = 1u, beta = 1.66
Charge pump
lMod = 10, lModS = 1, cpCap = 100f
pInc = 6.8, pInc2 = 10
nInc = 8, nInc2 = 6
Delay element (Delay line was 8 delay elements in series)
WDelay1 = 1.25, WDelay2 = 2, WDelay3 = 2, WDelay4 = 0.09, WDelay5 = 0.433, dbeta = 1.66
What I learned
What I learned
Skills Exercised/Gained
Skills Exercised/Gained
Cadence schematic design and simulation for 45 nm CMOS circuits
Testbench creation for functional and noise performance verification
Transistor-level circuit design (PFD, charge pump, voltage-controlled delay line)
Noise analysis and jitter characterization under supply/input interference
Parameter tuning (current mirrors, capacitor sizing) for gain and stability
Understanding and applying loop dynamics in feedback timing systems
Tradeoff evaluation between power, jitter, duty-cycle distortion, and lock range
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