PRE_DFT_TO_POST_DFT
# MAKE MEMORIES AS BLACK BOXES
# mem_list should contain list of all memories
foreach mem $mem_list {
puts $mem
add_notranslate_module $mem -both
}
# MAKE IPs AS BLACK BOXES
# ip_list should contain list of all IPs
foreach ip $ip_list {
puts $ip
add_notranslate_module $ip -both
}
# Read golden and revised netlists
read_design -uncompress $golden_verilog_file -verilog -golden -keep_unreach -append -ROot $DESIGN
read_design -uncompress $revised_verilog_file -verilog -revised -keep_unreach -append -ROot $DESIGN
set_root_module $DESIGN -golden
set_root_module $DESIGN -revised
## EXCEPTIONs TO DISABLE TEST LOGIC
##############################################################
# Procs to add pin constraints
proc find_and_add_pin_constraints {{constraint} {port} {netlist}} {
if { [find -Port -Input $port $netlist] != "" } {
puts "INFO: setting add_pin_constraints $constraint $port $netlist"
add_pin_constraints $constraint $port $netlist
}
}
proc find_and_add_ignored_inputs {{pin} {temp1} {module} {netlist}} {
if { [find -Module $module $netlist] != "" } {
puts "INFO: setting add_ignored_inputs $pin -module $module $netlist"
add_ignored_inputs $pin -module $module $netlist
}
}
# Adding pin constraints on TEST_* ports
find_and_add_pin_constraints 0 TEST__SE -revised
find_and_add_pin_constraints 0 TEST__CLK_GATE_DISABLE -revised
find_and_add_pin_constraints 0 TEST__DAX_CLOCK -revised
find_and_add_pin_constraints 0 TEST__COMPR -revised
find_and_add_pin_constraints 0 TEST__WRP_EXTEST -revised
find_and_add_pin_constraints 0 TEST__WRP_BYPASS -revised
find_and_add_pin_constraints 0 TEST__WRP_INTEST -revised
find_and_add_pin_constraints 0 TEST__WRP_DED_CAP_OUT -revised
find_and_add_pin_constraints 0 TEST__WRP_DED_CAP_IN -revised
find_and_add_pin_constraints 0 TEST__*SEL* -revised
find_and_add_pin_constraints 0 TEST__211*SIN* -revised
find_and_add_pin_constraints 0 TEST__DFT_CLK -revised
find_and_add_pin_constraints 0 TEST__LBIST_ACTIVE -golden
find_and_add_pin_constraints 0 TEST__LBIST_ACTIVE -revised
find_and_add_pin_constraints 0 TEST__MEM_ATPG_ACTIVE -revised
find_and_add_pin_constraints 0 TEST__MEM_CLK_GATE_DISABLE -revised
find_and_add_pin_constraints 0 TEST__MEM_LSI_TMG_MODE* -revised
find_and_add_pin_constraints 0 TEST__MEM_PBIST* -revised
find_and_add_pin_constraints 0 TEST__REDN_COL_DATA_IN* -revised
find_and_add_pin_constraints 0 TEST__REDN_COL_SHIFT_EN* -revised
find_and_add_pin_constraints 0 TEST__REDN_MBR_SHIFT* -revised
find_and_add_pin_constraints 0 TEST__REG_MEM_BYPASS -revised
find_and_add_pin_constraints 0 TEST__UNREG_MEM_BYPASS -revised
find_and_add_pin_constraints 0 TEST__TDR_CAPTURE -golden
find_and_add_pin_constraints 0 TEST__TDR_CAPTURE -revised
find_and_add_pin_constraints 1 TEST__TDR_RST -golden
find_and_add_pin_constraints 1 TEST__TDR_RST -revised
find_and_add_pin_constraints 0 TEST__TDR_SHIFT -golden
find_and_add_pin_constraints 0 TEST__TDR_SHIFT -revised
find_and_add_pin_constraints 0 TEST__TDR_UPDATE -revised
find_and_add_pin_constraints 0 TEST__CKMUX_OVERRIDE -revised
find_and_add_pin_constraints 0 TEST__CKMUX_TST_* -revised
find_and_add_pin_constraints 0 TEST__PDPR_TDR_SIN* -revised
find_and_add_pin_constraints 0 TEST__CCB_RESET_OVERRIDE -revised
find_and_add_pin_constraints 0 TEST__CLK_SEL_OVERRIDE -revised
find_and_add_pin_constraints 0 TEST__CKMUX_TST_S0_0 -revised
find_and_add_pin_constraints 0 TEST__CKMUX_TST_S1_0 -revised
find_and_add_pin_constraints 0 TEST__DRV_ENABLE -revised
find_and_add_pin_constraints 0 TEST__REI_ACT_MBR -revised
find_and_add_pin_constraints 0 TEST__ASYNC_DISABLE -revised
find_and_add_pin_constraints 0 TEST__ASYNC_DISABLE -golden
# Adding ignore inputs on Memory pins
find_and_add_ignored_inputs TEST__SIN* -module M3* -both
find_and_add_ignored_inputs TEST__TDR_SIN* -module M3* -both
find_and_add_ignored_inputs MEM_PD211HC_TMG_MODE* -module M3* -both
find_and_add_ignored_inputs ROW_REDN_SHIFT -module M3* -both
find_and_add_ignored_inputs COL_REDN_IN -module M3* -both
find_and_add_ignored_inputs TEST__XBLOCK_TDF_ONLY -module M3* -both
find_and_add_ignored_inputs ROW_REDN_IN -module M3* -both
find_and_add_ignored_inputs MEM_SRF211HC_TMG_MODE* -module M3* -both
find_and_add_ignored_inputs MEM_SP111HC_TMG_MODE* -module M3* -both
find_and_add_ignored_inputs MEM_PSP111HD_TMG_MODE* -module M3PSP111* -both
##############################################################
POST_DFT_TO_POST_LAYOUT
#leq_mapping.tcl
# MAKE MEMORIES AS BLACK BOXES
# mem_list should contain list of all memories
foreach mem $mem_list {
puts $mem
add_notranslate_module $mem -both
}
# MAKE IPs AS BLACK BOXES
# ip_list should contain list of all IPs
foreach ip $ip_list {
puts $ip
add_notranslate_module $ip -both
}
# Read golden and revised netlists
read_design -uncompress $golden_verilog_file -verilog -golden -keep_unreach -append -ROot $DESIGN
read_design -uncompress $revised_verilog_file -verilog -revised -keep_unreach -append -ROot $DESIGN
set_root_module $DESIGN -golden
set_root_module $DESIGN -revised
# Read MBIT mapping file (Example map.mp part of the deliverables)
source <DESIGN>.map.mp
# Source LEQ mapping file (Example leq_mapping.tcl part of the deliverables)
source leq_mapping.tcl
######## BELOW STEPS TO DISABLE TEST LOGIC ########
# To disable the TEST SI paths
add_pin_constraints 0 TEST__SE -golden
add_pin_constraints 0 TEST__SE -revised
# Source <DESIGN>.staVariables.tcl (Example staVariables.tcl part of the deliverables)
source <DESIGN>.staVariables.tcl
if { [info exists sri_ctrl_regs(int_ltest_en)]} {
foreach testreg $sri_ctrl_regs(int_ltest_en) {
add_instance_constraints 0 $testreg -revised
add_instance_constraints 0 $testreg -golden
}
}
if { [info exists sri_ctrl_regs(ext_ltest_en)]} {
foreach testreg $sri_ctrl_regs(ext_ltest_en) {
add_instance_constraints 0 $testreg -revised
add_instance_constraints 0 $testreg -golden
}
}
# Code to disable RSQ logic
set myloop 0
while { [ find -hier -instance "TEST__CKGT_$myloop" -gold ] != "" } {
echo "INFO: Forcing gold TEST__CKGT_$myloop to a 1"
add_instance_constraints 1 TEST__CKGT_$myloop -replace -gold
if { [ find -hier -instance "TEST__CKGT_$myloop" -revised ] != "" } {
echo "INFO: Forcing revised TEST__CKGT_$myloop to a 1"
add_instance_constraints 1 TEST__CKGT_$myloop -replace -revised
} else {
echo "ERROR: TEST__CKGT_$myloop exists in Golden and not in Revised"
}
incr myloop
}
# Code to ignore the DFT lockup latches added by rtl compiler
set StdCellLib(FlopInputPins) d
if { [find -hier -instance DFT_lockup_g* -revised] != "" } {
foreach pin $StdCellLib(FlopInputPins) {
add_primary_input DFT_lockup_g*/$pin -pin -revised
add_ignored_inputs DFT_lockup_g*/$pin -all -revised
}
}
if { [find -hier -instance DFT_lockup_g* -gold] != "" } {
foreach pin $StdCellLib(FlopInputPins) {
add_primary_input DFT_lockup_g*/$pin -pin -gold
add_ignored_inputs DFT_lockup_g*/$pin -all -gold
}
}
set latchInstNameList [ list \
*Q_MUXD_LOCKUP \
LOCKUP* \
*_lockuplatch* \
*_lockup_latchn_* \
]
foreach latchInstName $latchInstNameList {
if { [find -instance $latchInstName -revised -HIERarchical] != "" } {
foreach pin $StdCellLib(FlopInputPins) {
add_primary_input ${latchInstName}/$pin -pin -revised
add_ignored_inputs ${latchInstName}/$pin -all -revised
}
}
if { [find -instance $latchInstName -gold -HIERarchical] != "" } {
foreach pin $StdCellLib(FlopInputPins) {
add_primary_input ${latchInstName}/$pin -pin -gold
add_ignored_inputs ${latchInstName}/$pin -all -gold
}
}
}
# To identify the MBIT flops
set_multibit_option -prefix "CDN_MBIT_" -delimiter "_MB_"