PN85.2

newgrp design_apd

cd /project/mercury

/bin/bash

. /project/mercury/bin/chip_env -proj_dir PN85.2.dft_iter -prog_desc PN85.2

export DROP_DATA=/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft 

export MY_BLOCK=<your block name here - see the list below>

export MY_BLOCK_ROOT=$BLOCKPATH/$MY_BLOCK

/project/mercury/bin/mercury_block_setup

cd $GEV_PROJECT_ROOT/user/$USER/$PROJECT_DIR/impl/$MY_BLOCK

Blocks Dropped:
    hm_ae
    hm_be
    hm_clipi
    hm_clipo
    hm_conv_n
    hm_conv_s
    hm_dl
    hm_efr_n
    hm_efr_s
    hm_fh_n
    hm_fh_s
    hm_grad
    hm_iop
    hm_l1dl
    hm_l1ul
    hm_mac
    hm_pss
    hm_ulcap
    hm_xlgx
    pcie_ss_pcie_0
    pss_subsys_nokmercury

NOTE FROM : Matthew 

We have prepared a block drop for PN85.2.  The drop information and the blocks dropped are below.  Our expectation is that we will want to try to cubby these blocks in order to do a top level timing run with it probably in 3-4 weeks. To that end, I did try to make sure that all the pins are legal.  Please let me know if you find some that are not (but obviously ignore MIN-PIN_SPACING errors as those are fake).  Blocks are still sized somewhat aggressively but they are different with aspect ratio changes from the previous drop.  We will want to see whether or not these will build before committing to growth. Attached is a picture of the top level floorplan.

hm_fh_n/hm_fh_s

I have created the following directory:

/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_hm_fh_w_size_ok

It contains the two blocks with the extensive set_false_path commands in their sdc files.

The updated files are:

hm_fh_n/hm_fh_n.sdc

hm_fh_n/hm_fh_n_weakbit_mode.sdc

and

hm_fh_s/hm_fh_n.sdc

hm_fh_s/hm_fh_n_weakbit_mode.sdc

There are two additional files in each directory:

hm_fh_n/hm_fh_n.size_ok_list

hm_fh_n/customConfigFile.tcl

and

hm_fh_s/hm_fh_s.size_ok_list

hm_fh_s/customConfigFile.tcl

The supported method for using these files is to populate the:

source/customSupportDir/

directory with the: 

customConfigFile.tcl

<block>.size_ok_list

 files in your blockbuild area.  

Let me know if you have any questions.

pcie_ss_pcie_0

 I have created the following directory:

/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_pcie_ss_pcie_0_w_size_ok/

It contains the pcie_ss_pcie_0 block drop with two additional files:

pcie_ss_pcie_0.size_ok_list

customConfigFile.tcl

Please kick off an experimental run populating these files in the:

source/customSupportDir

directory.  Let me know if you have any questions or run into any issues.

Matthew

Actually it turns out that all of those pins on the left are disconnected at the top level.  This is the problem.  Here is another picture after I placed all the stdCellInstances in the their appropriate block:

At the top level they are connected to a bunch of SYNOPSYS_UNCONNECTED nets.  The constraints should have very loose constraints on these pins but maybe that's not enough.

I generated a version of the PCIE pins that has lal the pins in the center if you want to try that:

The pin file is here: /project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft/pcie_pin_center.ptn

Hm_mac : 

Hi Sai and Mahesh,

I have created the following updated drop for the hm_mac block:

/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_hm_mac_w_gen_clk_update

It has been updated to include div2 generated clocks that should hopefully have a very short route:

ck_pcs_rx*_div2_100G

ck_pcs_tx*_div2_100G

The wild cards are 0-3, so eight additional clocks.

Please start new builds with these updates.  Your current build data should be valid for placement/route analysis as I don't believe these updates will drastically change the overall build.

Thanks,

Woody

hm_pss:

Hi team,

I have created an updated clock_con file for this block:

hm_pss.clock_con.tcl

It can be found in the following directory:

/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_hm_pss_updated_clock_con_file

Please swap this clock_con file into your current build area/step and continue with your build.

Thanks,

Woody

pcie_ss_pcie_0

Hi Mahesh,

I've moved these "axi*" ports to the top of the pcie_ss_pcie_0 block (as can be seen in the attached picture), and placed them in a partition pin file here:

-rw-rw-r-- 1 rbassett design_apd 921209 Sep 25 16:55 /project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_pcie_ss_pcie_0_update_pin_locations/pcie_ss_pcie_0/pcie_ss_pcie_0.pin_plan.ptn

Hope that helps,

Rob

pss_subsys_nokmercury 

Hi Mahesh,

I've moved these "s_nokdtss_*" ports to a closer location to the hm_pss block (in the green circle in the attached picture) , and placed them in a partition pin file here:

-rw-rw-r-- 1 rbassett design_apd 1669007 Sep 25 16:55 /project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_pss_subsys_nokmercury_update_pin_locations/pss_subsys_nokmercury/pss_subsys_nokmercury.pin_plan.ptn

Please let me know if you have any trouble loading them.

Thanks,

Rob

Hm_mac:

Hi team,

A new hm_mac.clock_con.tcl file has been generated with updated clock uncertainty constraints to address the overly conservative uncertainty calculations:

I can be found in:

/project/mercury/source/PN85.2/80_blockdrop/PN85.2.dft_hm_mac_w_clock_con_update/hm_mac/hm_mac.clock_con.tcl

Please update your build with the new file.

Thanks,

Woody Salcido