"hm_io_e"
#######################FILES DELIVERED#######################
1. list_of_signal_bumps - Add to source directory so they are set dont_touch and no cells/buffers added
2. list_of_dont_touch_signals - Custom routes and internal IO bus nets, should not be routed in place and route
[ --> we should add the dont touch signals to port ISO exlude list
--> skip routing should be added
--> Antenna should be switched off
]
3. list_of_ref_clk_ports - Analog custom route, should not be routed in place and route
4. <BLOCK>_globalNetConnect.tcl - Power/Ground connection for io pads, invs flow
5. <BLOCK>_cal_drc_include_file - To be added for avo drc checks
6. <block>_<milestone>_<date>.def.gz
7. <block>_<milestone>_<date>.v.gz
8. <block>_<milestone>_<date>.lef
9. Pad_Block_README.txt
#######################GENERAL GUIDELINES FOR FLOORPLAN STAGE#######################
1. For 5nm SOIC, 3nm and newer technologies follow the pad block automation flow for placement/routing blockage insertion, macro placement, power mesh insertion, context/tap and border cell insertion, analog nets routing and core pin legalization/placement. For any pad block automation related questions contact Mohit Verma <mohit.verma@broadcom.com> and AnandBabu <anandbabu.gs@broadcom.com>.
2. For 5nm SOIC, 3nm and newer technologies Top level floorplanner must use the bump lef file from the floorplan stage output. This lef will have both bump information and also core pins legalized.
3. For regular 5nm, 7nm and older technologies the def we deliver will have the power mesh inserted, analog nets routed and core pins placed.
#######################GENERAL GUIDELINES FOR PnR (Prep and beyond) STAGE#######################
1. All the signals in list_of_dont_touch_signals are either internal bus nets or analog nets. They are either routed in source DEF (for regular 5nm and older technologies) or routed during the block build floorplan stage (for 5nm SOIC, 3nm and newer technologies). Please do not re-route or add any add buffers or port/clock isolation on these nets in place and route.
2. Reference clock receiver BCM*HCSL_D18NH_ACCKIN analog pins are the REFCLK. Analog path should be left unbuffered/routed wide. Do not add buffers or port/clock isolation.
Pin names: CLK, CLK_N, MUX_CLK, MUX_CLK_N
REFCLKs - unbuffered to die edge
REFCLKs - Wide routes to die edge
If an analog pin's signal needs to enter the digital power domain, a CDM1000* cell must be used.
3. VTMON IP. Do not add portisolation or buffer vmon_* and *remote_sensor* signals. All these are analog and are either routed in source DEF (for regular 5nm and older technologies) or routed during the block build floorplan stage (for 5nm SOIC, 3nm and newer technologies)..
4. For blocks using BCM*FF*XD18DFT_DXXH/V_DDRV as part of GPIO segment, make sure the ddrv50 and ddrv200 pins are not buffered or connected to any standard cell.
5. *globalNetConnect.tcl should be sourced in invs and aa.
6. *cal_drc_include_file should be used for avo drc checks.
7. Make sure in addition to the clock nets defined in the SDC file (provided by the DI), all below paths are CTSed in pad blocks. They should be CTSed, Routed in NDRA or above with shields.
REFCLKs - Any digital branch from analog REFCLK pins should be through CDM1000 cell
Sbus Clks - Wide & Shielded - sbus_clk_<in|out>
Sbus Clks - Wide & Shielded - sbus_bist_stat_<in|out>
JTAG Clks - Wide & Shielded - TEST__<CLOCK|UPDATE>_DR (e.g. TEST__BUFFERED_CLK)
Test Shift Clks - TEST__*SHIFT_CLK
BCM*HCSL_D18NH_ACCKIN - TEST__ACEXTEST_CAPTURE
ds0*_clock_control* - TEST__EXECUTE, TEST__HALTED
LIB_VTMON_* - i_ADC_clk, pclk
ds0*_sbus2apb_* - sensor_clk, pclk
BCM*HSTL_PMNH_PVT15_DRV/TERM - CLK
Functional Clks - Wide & Shielded - To Clock Observation
Functional Clks - Wide & Shielded - To|From IP
8. Any clock nets should routed with NDR rule. Clock nets are nets that are connecting any clock pins. These nets may not be defined in SDC file.
9. Ensure prep/611_cal_drc_base_layers_gc_filled step is drc clean before proceeding with rest of the block build flow.
10. Ensure to use original netlist for invs/avo formality checks. This original netlist can be obtained from the top level floorplanner.
#######################GENERAL GUIDELINES FOR POST AVO FLOORPLAN CHECKS#######################
1. Make sure the pad block's final avo database is reviewed by respective IO/IP owners. This should be done on both PN99 and FN avo database.
2. Make sure pathfinder ESD check is run on all the pad blocks and the results are reviewed with Chester Leung <chester.leung@broadcom.com>. This is mandatory to meet ESD silicon quality. This should be run on both PN99 and FN avo database. More details on pathfinder checks can be found in "https://confluence.broadcom.net/display/CEGIO/ESD+and+Latch-up+Prevention+CAD+Verification" website.
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