Structural Modeling In VHDL

VHDL Modularity with Components

• modularity is achieved via the use of packages, components and functions
• The approach to use a component
  1. name the module you plan to describe (the entity)
  2. describe what the module will do (the architecture)
  3. let the program know the module exists and can be used (component declaration)
  4. use the module in your code (component instantiation, or mapping)
• The procedures for implementing a structural VHDL design:

Step 1. Generate the top-level entity declaration

Step 2. Declare the lower-level design units used in design

Step 3. Declare required internal signals used to connect the design units

Step 4. Instantiate the design units

Generic Map

• Write code that is generic.
  • routine that performs a certain task on an input array of a generic size

Important Points

• Structural modeling in VHDL supports hierarchical design concepts. The ability to abstract digital circuits to higher levels is the key to understanding and designing complex digital circuits
• Digital design using schematic capture is an outdated approach: you should resist the inclination and/or directive at all costs
• The VHDL structural model supports the reuse of design units. This includes units you have previously designed as well as the ability to use predefined module libraries