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Standard Models in VHDL Architectures
Standard Models in VHDL Architectures
Data-flow Style Architecture
- Circuits are described by showing the input and output relationships between the various built-in components of the VHDL language (AND, OR, XOR, etc.)
- describes how the circuit should look in terms of logic gates
- concurrent signal assignment, conditional signal assignment and selected signal assignment
- for small and relatively simple circuits
Behavioral Style Architecture
- provides no details as to how the design is implemented in actual hardware
- models how the circuit outputs will react to the circuit inputs
- describes how the circuit should behave
- uses process statements
Process Statement
- a concurrent statement identified by its label, its sensitivity list, a declaration area and a begin-end area containing instructions executed sequentially
Sequential Statements
- Signal Assignment Statement
- “<=”
- if Statement
- create a branch in the execution flow of the sequential statements
- case Statement
- The statements executed are determined by the first when branch to evaluate as true
Caveats Regarding Sequential Statements
- VHDL is not programming: VHDL is hardware design
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