Concurrent Statements

• VHDL has the ability to execute a virtually unlimited number of statements at the same time and in a concurrent manner (in other words, in parallel)

Signal Assignment Operator “<=”

• the signal on the left-hand side of the signal assignment operator is dependent upon the signals on the right-hand side of the operator
  • "G <= A AND B;” indicates that the value of the signal named G represents an AND logic operation between the signals A and B

Concurrent Signal Assignment Statements

• <target> <= <expression>;
  • the target is a signal that receives the values of the expression. An expression is defined by a constant, by a signal, or by a set of operators that operate on other signals

Conditional Signal Assignment when

• used to describe statements that have only one target but have more than one associated expression assigned to the target
• The condition is based upon the state of some other signals in the given circuit
• individual conditions are evaluated sequentially until the first condition is true, and then is the only assignment for the statement