Lab 6

Lab 6: Video Game "PONG"

Main Code:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pong IS PORT ( clk_50MHz : IN STD_LOGIC; -- system clock VGA_red : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); -- VGA outputs VGA_green : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); VGA_blue : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); VGA_hsync : OUT STD_LOGIC; VGA_vsync : OUT STD_LOGIC; Sw: in STD_LOGIC_VECTOR(6 downto 0); ADC_CS : OUT STD_LOGIC; -- ADC signals ADC_SCLK : OUT STD_LOGIC; ADC_SDATA1 : IN STD_LOGIC; ADC_SDATA2 : IN STD_LOGIC; btn0 : IN STD_LOGIC); -- button to initiate serveEND pong;
ARCHITECTURE Behavioral OF pong IS SIGNAL ck_25 : STD_LOGIC := '0'; -- 25 MHz clock to VGA sync module -- internal signals to connect modules SIGNAL S_red, S_green, S_blue : STD_LOGIC; SIGNAL S_vsync : STD_LOGIC; SIGNAL S_pixel_row, S_pixel_col : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL batpos : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL serial_clk, sample_clk : STD_LOGIC; SIGNAL adout : STD_LOGIC_VECTOR (11 DOWNTO 0); SIGNAL count : STD_LOGIC_VECTOR (9 DOWNTO 0); -- counter to generate ADC clocks COMPONENT adc_if IS PORT ( SCK : IN STD_LOGIC; SDATA1 : IN STD_LOGIC; SDATA2 : IN STD_LOGIC; CS : IN STD_LOGIC; data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; COMPONENT bat_n_ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(9 DOWNTO 0); bat_x : IN STD_LOGIC_VECTOR (9 DOWNTO 0); serve : IN STD_LOGIC; Sw: in STD_LOGIC_VECTOR(6 downto 0); red : OUT STD_LOGIC; green : OUT STD_LOGIC; blue : OUT STD_LOGIC ); END COMPONENT; COMPONENT vga_sync IS PORT ( clock_25MHz : IN STD_LOGIC; red : IN STD_LOGIC; green : IN STD_LOGIC; blue : IN STD_LOGIC; red_out : OUT STD_LOGIC; green_out : OUT STD_LOGIC; blue_out : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END COMPONENT;BEGIN -- Process to generate clock signals ckp : PROCESS BEGIN WAIT UNTIL rising_edge(clk_50MHz); ck_25 <= NOT ck_25; -- 25MHz clock for VGA modules count <= count + 1; -- counter to generate ADC timing signals END PROCESS; serial_clk <= NOT count(4); -- 1.5 MHz serial clock for ADC ADC_SCLK <= serial_clk; sample_clk <= count(9); -- sampling clock is low for 16 SCLKs ADC_CS <= sample_clk; -- Multiplies ADC output (0-4095) by 5/32 to give bat position (0-640) batpos <= ('0' & adout(11 DOWNTO 3)) + adout(11 DOWNTO 5); -- set least significant bits of VGA video to '0' VGA_red(1 DOWNTO 0) <= "00"; VGA_green(1 DOWNTO 0) <= "00"; VGA_blue(0) <= '0'; adc : adc_if PORT MAP(-- instantiate ADC serial to parallel interface SCK => serial_clk, CS => sample_clk, SDATA1 => ADC_SDATA1, SDATA2 => ADC_SDATA2, data_1 => OPEN, data_2 => adout ); add_bb : bat_n_ball PORT MAP(--instantiate bat and ball component v_sync => S_vsync, pixel_row => S_pixel_row, pixel_col => S_pixel_col, bat_x => batpos, serve => btn0, red => S_red, green => S_green, Sw => Sw, blue => S_blue ); vga_driver : vga_sync PORT MAP(--instantiate vga_sync component clock_25MHz => ck_25, red => S_red, green => S_green, blue => S_blue, red_out => VGA_red(2), green_out => VGA_green(2), blue_out => VGA_blue(1), pixel_row => S_pixel_row, pixel_col => S_pixel_col, hsync => VGA_hsync, vsync => S_vsync ); VGA_vsync <= S_vsync; --connect output vsyncEND Behavioral;

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adc_if IS PORT ( SCK : IN STD_LOGIC; -- serial clock that goes to ADC SDATA1 : IN STD_LOGIC; -- serial data channel 1 SDATA2 : IN STD_LOGIC; -- serial data channel 2 CS : IN STD_LOGIC; -- chip select that initiates A/D conversion data_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- parallel 12-bit data ch1 data_2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); -- parallel 12-bit data ch2END adc_if;
ARCHITECTURE Behavioral OF adc_if IS SIGNAL pdata1, pdata2 : std_logic_vector (11 DOWNTO 0); -- 12-bit shift registersBEGIN -- this process waits for CS=0 and then clocks serial data from ADC into shift register -- MSBit first. After 16 SCK's, four leading zeros will have fallen out of the most significant -- end of the shift register and the register will contain the parallel12-bit data adpr : PROCESS BEGIN WAIT UNTIL falling_edge (SCK); IF CS = '0' THEN pdata1 <= pdata1 (10 DOWNTO 0) & SDATA1; pdata2 <= pdata2 (10 DOWNTO 0) & SDATA2; END IF; END PROCESS; -- this process waits for rising edge of CS and then loads parallel data -- from shift register into appropriate output port sync : PROCESS BEGIN WAIT UNTIL rising_edge (CS); data_1 <= pdata1; data_2 <= pdata2; END PROCESS;END Behavioral;

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bat_n_ball IS PORT ( v_sync : IN STD_LOGIC; pixel_row : IN STD_LOGIC_VECTOR(9 DOWNTO 0); pixel_col : IN STD_LOGIC_VECTOR(9 DOWNTO 0); bat_x : IN STD_LOGIC_VECTOR (9 DOWNTO 0); -- current bat x position serve : IN STD_LOGIC; -- initiates serve red : OUT STD_LOGIC; Sw: in STD_LOGIC_VECTOR(6 downto 0); green : OUT STD_LOGIC; blue : OUT STD_LOGIC );END bat_n_ball;
ARCHITECTURE Behavioral OF bat_n_ball IS CONSTANT bsize : INTEGER := 10; -- ball size in pixels SIGNAL bat_w : INTEGER := 75; -- bat width in pixels CONSTANT bat_h : INTEGER := 5; -- bat height in pixels SIGNAL score : INTEGER :=0; -- distance ball moves each frame CONSTANT ball_speed : STD_LOGIC_VECTOR (9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR (6, 10); SIGNAL ball_on : STD_LOGIC; -- indicates whether ball is at current pixel position SIGNAL bat_on : STD_LOGIC; -- indicates whether bat at over current pixel position SIGNAL game_on : STD_LOGIC := '0'; -- indicates whether ball is in play -- current ball position - intitialized to center of screen SIGNAL ball_x : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(320, 10); SIGNAL ball_y : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(240, 10); -- bat vertical position CONSTANT bat_y : STD_LOGIC_VECTOR(9 DOWNTO 0) := CONV_STD_LOGIC_VECTOR(400, 10); -- current ball motion - initialized to (+ ball_speed) pixels/frame in both X and Y directions SIGNAL ball_x_motion, ball_y_motion : STD_LOGIC_VECTOR(9 DOWNTO 0) := ball_speed;BEGIN red <= NOT bat_on; -- color setup for red ball and cyan bat on white background green <= NOT ball_on; blue <= NOT ball_on; -- process to draw round ball -- set ball_on if current pixel address is covered by ball position balldraw : PROCESS (ball_x, ball_y, pixel_row, pixel_col) IS VARIABLE vx, vy : STD_LOGIC_VECTOR (9 DOWNTO 0); BEGIN IF pixel_col <= ball_x THEN -- vx = |ball_x - pixel_col| vx := ball_x - pixel_col; ELSE vx := pixel_col - ball_x; END IF; IF pixel_row <= ball_y THEN -- vy = |ball_y - pixel_row| vy := ball_y - pixel_row; ELSE vy := pixel_row - ball_y; END IF; IF ((vx * vx) + (vy * vy)) < (bsize * bsize) THEN -- test if radial distance < bsize ball_on <= game_on; ELSE ball_on <= '0'; END IF; END PROCESS; -- process to draw bat -- set bat_on if current pixel address is covered by bat position batdraw : PROCESS (ball_x, pixel_row, pixel_col) IS VARIABLE vx, vy : STD_LOGIC_VECTOR (9 DOWNTO 0); BEGIN IF ((pixel_col >= ball_x - bat_w) OR (ball_x <= bat_w)) AND pixel_col <= ball_x + bat_w AND pixel_row >= bat_y - bat_h AND pixel_row <= bat_y + bat_h THEN bat_on <= '1'; ELSE bat_on <= '0'; END IF; END PROCESS; -- process to move ball once every frame (i.e. once every vsync pulse) mball : PROCESS VARIABLE temp : STD_LOGIC_VECTOR (10 DOWNTO 0); BEGIN WAIT UNTIL rising_edge(v_sync); IF serve = '1' AND game_on = '0' THEN -- test for new serve game_on <= '1'; ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels ELSIF ball_y <= bsize THEN -- bounce off top wall ball_y_motion <= ball_speed; -- set vspeed to (+ ball_speed) pixels ELSIF ball_y + bsize >= 480 THEN -- if ball meets bottom wall ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels game_on <= '0'; -- and make ball disappear bat_w <= 75; END IF; -- allow for bounce off left or right of screen IF ball_x + bsize >= 640 THEN -- bounce off right wall ball_x_motion <= (NOT ball_speed) + 1; -- set hspeed to (- ball_speed) pixels ELSIF ball_x <= bsize THEN -- bounce off left wall ball_x_motion <= ball_speed; -- set hspeed to (+ ball_speed) pixels END IF; -- allow for bounce off bat IF (ball_x + bsize/2) >= (ball_x - bat_w) AND (ball_x - bsize/2) <= (ball_x + bat_w) AND (ball_y + bsize/2) >= (bat_y - bat_h) AND (ball_y - bsize/2) <= (bat_y + bat_h) THEN ball_y_motion <= (NOT ball_speed) + 1; -- set vspeed to (- ball_speed) pixels bat_w<=bat_w-1; END IF; -- compute next ball vertical position -- variable temp adds one more bit to calculation to fix unsigned underflow problems -- when ball_y is close to zero and ball_y_motion is negative temp := ('0' & ball_y) + (ball_y_motion(9) & ball_y_motion); IF game_on = '0' THEN ball_y <= CONV_STD_LOGIC_VECTOR(440, 10); ELSIF temp(10) = '1' THEN ball_y <= (OTHERS => '0'); ELSE ball_y <= temp(9 DOWNTO 0); END IF; -- compute next ball horizontal position -- variable temp adds one more bit to calculation to fix unsigned underflow problems -- when ball_x is close to zero and ball_x_motion is negative temp := ('0' & ball_x) + (ball_x_motion(9) & ball_x_motion); IF temp(10) = '1' THEN ball_x <= (OTHERS => '0'); ELSE ball_x <= temp(9 DOWNTO 0); END IF; END PROCESS;END Behavioral;

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY vga_sync IS PORT ( clock_25MHz : IN STD_LOGIC; red : IN STD_LOGIC; green : IN STD_LOGIC; blue : IN STD_LOGIC; red_out : OUT STD_LOGIC; green_out : OUT STD_LOGIC; blue_out : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; pixel_row : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); pixel_col : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) );END vga_sync;
ARCHITECTURE Behavioral OF vga_sync IS SIGNAL h_cnt, v_cnt : STD_LOGIC_VECTOR (9 DOWNTO 0);BEGIN sync_pr : PROCESS VARIABLE video_on : STD_LOGIC; BEGIN WAIT UNTIL rising_edge(clock_25MHz); -- Generate Horizontal Timing Signals for Video Signal -- h_cnt counts pixels across line (800 total = 640 active + extras for sync and blanking) -- Active picture for 0 <= h_cnt <= 639 -- Hsync for 659 <= h_cnt <= 755 IF h_cnt >= 799 THEN h_cnt <= "0000000000"; ELSE h_cnt <= h_cnt + 1; END IF; IF (h_cnt >= 659) AND (h_cnt <= 755) THEN hsync <= '0'; ELSE hsync <= '1'; END IF; -- Generate Vertical Timing Signals for Video Signal -- v_cnt counts lines down screen (525 total = 480 active + extras for sync and blanking) -- Active picture for 0 <= v_cnt <= 479 -- Vsync for 493 <= h_cnt <= 494 IF (v_cnt >= 524) AND (h_cnt = 699) THEN v_cnt <= "0000000000"; ELSIF h_cnt = 699 THEN v_cnt <= v_cnt + 1; END IF; IF (v_cnt >= 493) AND (v_cnt <= 494) THEN vsync <= '0'; ELSE vsync <= '1'; END IF; -- Generate Video Signals and Pixel Address IF (h_cnt <= 639) AND (v_cnt <= 479) THEN video_on := '1'; ELSE video_on := '0'; END IF; pixel_col <= h_cnt; pixel_row <= v_cnt; -- Register video to clock edge and suppress video during blanking and sync periods red_out <= red AND video_on; green_out <= green AND video_on; blue_out <= blue AND video_on; END PROCESS;END Behavioral;

Constraint File:

create_clock -name clk_50MHz -period 20.00 [get_ports clk_50MHz]
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports clk_50MHz]
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_hsync }]; #IO_L4P_T0_15 Sch=vga_hs
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_vsync }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_blue[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
#set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVCMOS33} [get_ports {VGA_blue[2]]
#set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports {VGA_blue[3]]
set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_red[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
#set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {VGA_red[3]}]
set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_green[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
#set_property -dict {PACKAGE_PIN A6 IOSTANDARD LVCMOS33} [get_ports {VGA_green[3]}]
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA1 }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ADC_SDATA2 }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ADC_SCLK }]; #IO_L18N_T2_A23_15 Sch=ja[4]
set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ADC_CS }]; #IO_L20N_T3_A19_15 Sch=ja[1]
set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btn0 }]; #IO_L9P_T1_DQS_14 Sch=btnc

set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {Sw[0]}]set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {Sw[1]}]set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {Sw[2]}]set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {Sw[3]}]set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {Sw[4]}]set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {Sw[5]}]set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {Sw[6]}]

Take Aways:

Our group was able to successfully create a pong game using the FPGA, Pmod, and potentiometer. We programmed an interactive game a player could use and play by using a paddle to keep the ball in bounds. We were able to see a fun application of the FPGA board. It also demonstrated the scope of things you can accomplish with an FPGA board.

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