Variables and Assignment Operator “:=”

• Variables can only be declared and used inside of processes, functions and procedures
• all statements appearing in the body of a process are sequential
• The signal assignment operator, <=, is used to transfer the value of one signal to another while dealing with signal data objects
• When working with variables, the assignment operator := is used to transfer the value of one variable data object to another

Signals vs. Variables

• Signals:
  • represent a wire or some type of physical connection in a design
  • represent a means to interface VHDL modules which include connections to the outside world
  • In terms of circuit simulation, signals can be scheduled to take on multiple values at specific times in the simulation
• events can be scheduled for signals while for variables, they cannot
• Assignments made to signals inside a process are actually only scheduled when the same process is completed. The actual assignment is not made until after the process terminates
• `multiple signal assignments can be made to the same signal during the execution of a process without generating any type of synthesis error
• When a variable is assigned a value inside of a process, the assignment is immediate and the newly assigned value can be used immediately inside of the process. In other words, the variable assignment is not scheduled like it was for the signal
• Variables should only be used as iteration counters in loops or as temporary values when executing an algorithm that performs some type of calculation

Standard Data Types

User-Defined Types

• VHDL allows you to define your own data type
  • EX: type my type is range 0 to 100;

Commonly Used Types

Integer Types

• aid in algorithmic-type VHDL code
• −(2³¹) to +(2³¹ − 1)

signed and unsigned Types

• signed value range: −2^N−1 to 2^N−1 − 1
• unsigned value range 0 to 2^N − 1
• used for internal vari- ables as well as for entity ports

std logic Types