Lab 5

Lab 5: DAC Siren

Main Code:

library IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
ENTITY siren ISPORT (BTN0: in STD_LOGIC;SW0 : IN STD_LOGIC;SW1 : IN STD_LOGIC;SW2 : IN STD_LOGIC;SW3 : IN STD_LOGIC;SW4 : IN STD_LOGIC;SW5 : IN STD_LOGIC;SW6 : IN STD_LOGIC;SW7 : IN STD_LOGIC;clk_50MHz : IN STD_LOGIC; -- system clock (50 MHz)dac_MCLK : OUT STD_LOGIC; -- outputs to PMODI2L DACdac_LRCK : OUT STD_LOGIC;dac_SCLK : OUT STD_LOGIC;dac_SDIN : OUT STD_LOGIC);END siren;
ARCHITECTURE Behavioral OF siren ISCONSTANT lo_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (344, 14); -- lower limit of siren = 256 HzCONSTANT hi_tone : UNSIGNED (13 DOWNTO 0) := to_unsigned (687, 14); -- upper limit of siren = 512 Hzsignal wail_speed : UNSIGNED (7 DOWNTO 0) := to_unsigned (8, 8); -- sets wailing speed
COMPONENT dac_if ISPORT (SCLK : IN STD_LOGIC;L_start : IN STD_LOGIC;R_start : IN STD_LOGIC;L_data : IN signed (15 DOWNTO 0);R_data : IN signed (15 DOWNTO 0);SDATA : OUT STD_LOGIC);END COMPONENT;COMPONENT wail ISPORT (lo_pitch : IN UNSIGNED (13 DOWNTO 0);hi_pitch : IN UNSIGNED (13 DOWNTO 0);wspeed : IN UNSIGNED (7 DOWNTO 0);wclk : IN STD_LOGIC;audio_clk : IN STD_LOGIC;button_press : in STD_LOGIC;audio_data : OUT SIGNED (15 DOWNTO 0));END COMPONENT;SIGNAL tcount : unsigned (19 DOWNTO 0) := (OTHERS => '0'); -- timing counterSIGNAL data_L, data_R : SIGNED (15 DOWNTO 0); -- 16-bit signed audio dataSIGNAL dac_load_L, dac_load_R : STD_LOGIC; -- timing pulses to load DAC shift reg.SIGNAL slo_clk, sclk, audio_CLK : STD_LOGIC;BEGIN-- this process sets up a 20 bit binary counter clocked at 50MHz. This is used-- to generate all necessary timing signals. dac_load_L and dac_load_R are pulses-- sent to dac_if to load parallel data into shift register for serial clocking-- out to DACtim_pr : PROCESSBEGINWAIT UNTIL rising_edge(clk_50MHz);IF (tcount(9 DOWNTO 0) >= X"00F") AND (tcount(9 DOWNTO 0) < X"02E") THENdac_load_L <= '1';ELSEdac_load_L <= '0';END IF;IF (tcount(9 DOWNTO 0) >= X"20F") AND (tcount(9 DOWNTO 0) < X"22E") THENdac_load_R <= '1';ELSE dac_load_R <= '0';END IF;tcount <= tcount + 1;END PROCESS;dac_MCLK <= NOT tcount(1); -- DAC master clock (12.5 MHz)audio_CLK <= tcount(9); -- audio sampling rate (48.8 kHz)dac_LRCK <= audio_CLK; -- also sent to DAC as left/right clocksclk <= tcount(4); -- serial data clock (1.56 MHz)dac_SCLK <= sclk; -- also sent to DAC as SCLKslo_clk <= tcount(19); -- clock to control wailing of tone (47.6 Hz)wail_speed(0) <= SW0;wail_speed(1) <= SW1;wail_speed(2) <= SW2;wail_speed(3) <= SW3;wail_speed(4) <= SW4;wail_speed(5) <= SW5;wail_speed(6) <= SW6;wail_speed(7) <= SW7;
dac : dac_ifPORT MAP(SCLK => sclk, -- instantiate parallel to serial DAC interfaceL_start => dac_load_L, R_start => dac_load_R, L_data => data_L, R_data => data_R, SDATA => dac_SDIN );w1 : wailPORT MAP(lo_pitch => lo_tone, -- instantiate wailing sirenhi_pitch => hi_tone, wspeed => wail_speed, wclk => slo_clk, button_press => BTN0,audio_clk => audio_clk, audio_data => data_L);w2 : wailPORT MAP(lo_pitch => hi_tone, -- instantiate wailing sirenhi_pitch => lo_tone, wspeed => wail_speed, wclk => slo_clk, button_press => BTN0,
wail.vhd
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
-- Generates a "wailing siren" sound by instancing a "tone" module and modulating-- the pitch of the tone. The pitch is increased until it reaches hi_pitch and then-- decreased until it reaches lo_pitch and then increased again...etc.ENTITY wail ISPORT (lo_pitch : IN UNSIGNED (13 DOWNTO 0); -- lowest pitch (in units of 0.745 Hz)hi_pitch : IN UNSIGNED (13 DOWNTO 0); -- highest pitch (in units of 0.745 Hz)wspeed : IN UNSIGNED (7 DOWNTO 0); -- speed of wail in pitch units/wclkbutton_press : in STD_LOGIC;wclk : IN STD_LOGIC; -- wailing clock (47.6 Hz)audio_clk : IN STD_LOGIC; -- audio sampling clock (48.8 kHz)audio_data : OUT SIGNED (15 DOWNTO 0)); -- output audio sequence (wailing tone)END wail;
ARCHITECTURE Behavioral OF wail ISCOMPONENT tone ISPORT (clk : IN STD_LOGIC;pitch : IN UNSIGNED (13 DOWNTO 0);btn_press : in STD_LOGIC;data : OUT SIGNED (15 DOWNTO 0));END COMPONENT;SIGNAL curr_pitch : UNSIGNED (13 DOWNTO 0); -- current wailing pitchBEGIN-- this process modulates the current pitch. It keep a variable updn to indicate-- whether tome is currently rising or falling. Each wclk period it increments-- (or decrements) the current pitch by wspeed. When it reaches hi_pitch, it-- starts counting down. When it reaches lo_pitch, it starts counting upwp : PROCESSVARIABLE updn : std_logic;BEGINWAIT UNTIL rising_edge(wclk);IF curr_pitch >= hi_pitch THENupdn := '0'; -- check to see if still in rangeELSIF curr_pitch <= lo_pitch THENupdn := '1'; -- if not, adjust updnEND IF;IF updn = '1' THENcurr_pitch <= curr_pitch + wspeed; -- modulate pitch according toELSEcurr_pitch <= curr_pitch - wspeed; -- current value of updnEND IF;END PROCESS;tgen : tonePORT MAP(clk => audio_clk, -- instance a tone modulebtn_press => button_press,pitch => curr_pitch, -- use curr-pitch to modulate tonedata => audio_data);END Behavioral;
tone.vhd

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
-- Generates a 16-bit signed triangle wave sequence at a sampling rate determined-- by input clk and with a frequency of (clk*pitch)/65,536ENTITY tone ISPORT (clk : IN STD_LOGIC; -- 48.8 kHz audio sampling clockpitch : IN UNSIGNED (13 DOWNTO 0); -- frequency (in units of 0.745 Hz)btn_press : in STD_LOGIC;data : OUT SIGNED (15 DOWNTO 0)); -- signed triangle wave outEND tone;
ARCHITECTURE Behavioral OF tone ISSIGNAL count : unsigned (15 DOWNTO 0); -- represents current phase of waveformSIGNAL quad : std_logic_vector (1 DOWNTO 0); -- current quadrant of phaseSIGNAL index : signed (15 DOWNTO 0); -- index into current quadrant
signal data_sq:SIGNED(15 downto 0);signal data_tri:SIGNED(15 downto 0);
BEGIN-- This process adds "pitch" to the current phase every sampling period. Generates-- an unsigned 16-bit sawtooth waveform. Frequency is determined by pitch. For-- example when pitch=1, then frequency will be 0.745 Hz. When pitch=16,384, frequency-- will be 12.2 kHz.cnt_pr : PROCESSBEGINWAIT UNTIL rising_edge(clk);count <= count + pitch;END PROCESS;quad <= std_logic_vector (count (15 DOWNTO 14)); -- splits count range into 4 phasesindex <= signed ("00" & count (13 DOWNTO 0)); -- 14-bit index into the current phase-- This select statement converts an unsigned 16-bit sawtooth that ranges from 65,535-- into a signed 12-bit triangle wave that ranges from -16,383 to +16,383WITH quad SELECT data_sq <= to_signed(16383, 16) when "00",to_signed(-16383, 16) when "01", to_signed(16383,16) when "10",to_signed(-16383,16) when others;with quad select data_tri <= index when "00", 16383 - index when "01", 0 - index when "10", index - 16383 when others;--with quad select --data <= index WHEN "00", -- 1st quadrant --16383 - index WHEN "01", -- 2nd quadrant -- 0 - index WHEN "10", -- 3rd quadrant -- index - 16383 WHEN OTHERS; -- 4th quadranttone_select: processbegin if btn_press = '1' then data <= data_sq; else data <= data_tri; end if;end process;END Behavioral;
dac_if.vhd
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;
ENTITY dac_if ISPORT (SCLK : IN STD_LOGIC; -- serial clock (1.56 MHz)L_start : IN STD_LOGIC; -- strobe to load LEFT dataR_start : IN STD_LOGIC; -- strobe to load RIGHT dataL_data : IN SIGNED (15 DOWNTO 0); -- LEFT data (15-bit signed)R_data : IN SIGNED (15 DOWNTO 0); -- RIGHT data (15-bit signed)SDATA : OUT STD_LOGIC); -- serial data stream to DACEND dac_if;
ARCHITECTURE Behavioral OF dac_if ISSIGNAL sreg : STD_LOGIC_VECTOR (15 DOWNTO 0); -- 16-bit shift register to do-- parallel to serial conversionBEGIN-- SREG is used to serially shift data out to DAC, MSBit first.-- Left data is loaded into SREG on falling edge of SCLK when L_start is active.-- Right data is loaded into SREG on falling edge of SCLK when R_start is active.-- At other times, falling edge of SCLK causes REG to logically shift one bit left-- Serial data to DAC is MSBit of SREGdac_proc : PROCESSBEGINWAIT UNTIL falling_edge(SCLK);IF L_start = '1' THENsreg <= std_logic_vector (L_data); -- load LEFT data into SREGELSIF R_start = '1' THENsreg <= std_logic_vector (R_data); -- load RIGHT data into SREGELSEsreg <= sreg(14 DOWNTO 0) & '0'; -- logically shift SREG one bit leftEND IF;END PROCESS;SDATA <= sreg(15); -- serial data to DAC is MSBit of SREGEND Behavioral;

Take Aways

This lab helped the group to understand the conversion between digital to analog, using a DAC. This was accomplished by generating a bitstream from a digital audio. Lastly, we utilized the Pmod ports with DAC modules on the Nexys4 board in order to create the siren.

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