Simple Storage Elements Using VHDL
- Cross coupled cell forms a latch
- Clocking signal is added to the device in order to enhance its controllability
- Some type of pulse narrowing circuitry is added to the clocking signal to get to the flip-flop
- The flip-flop is nothing more than an edgesensitive bit-storage device
- The D flip flop (dff) can store a single bit
- The bit-storage capability in VHDL is implied by the way the VHDL code is interpreted
- If you have not specified what the output should be for every possible set of input conditions, the option taken by VHDL is to not change the current output. By definition, if the input changes to an unspecified state, the output remains unchanged
Inducing Memory: Data-flow vs. Behavioral Modeling
- Output changes only occur on a clock edge
Important Points
- Storage elements in VHDL are induced by not specifying output condi- tions for every possible input condition
- Unintended generation of storage elements is generally listed by the synthesizer as latch generation. Once again, latches are generated when there is an existing input condition to a circuit that does not have a corresponding output specification
- Memory elements can be induced by both data-flow and behavioral models
- If a signal declared in the entity declaration has a mode specifier of out, that signal cannot appear on the right-hand side of a signal assignment operator. This limitation is bypassed by using intermediate signals for any functional assignments and later assigning the intermediate signal to the output signal using a concurrent signal assignment statement
- The mode specification of buffer should be avoided in favor of inter- mediate signals