Synchronous Decade Counter

Synchronous Decimal Counter  

OR

Synchronous Decade Counter 

 A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. After reaching the count of “1001”, the counter recycles back to “0000”. We now have a decade orModulo-10 counter. It is also called as Divide-by-10 Counter.

Decade 4-bit Synchronous Counter

Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and then recycles to 0 again.  This is done by forcing the 1010 state back to the 0000 state.  This so called truncated sequence can be constructed by the following circuit. 

Note that FFA or FF0 has output QA = Q0, FFB or FF1 has QB = Q1, 

                   FFC or FF2 has QC = Q2 and FFD or FF3 has QD = Q3.

From the sequence in the Figure, we notice that:

• Q0 toggles on each clock pulse.

• Q1 changes on the next clock pulse each time Q0=1 and Q3=0.

• Q2 changes on the next clock pulse each time Q0=Q1=1.

• Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1

(count 7), or then Q0=1 and Q3=1 (count 9).

FF0 (Q0) toggles on each clock pulse.

J0 = K0 = 1

FF1 (Q1) changes on the next clock pulse each time Q0=1 and Q3=0.

J1 = K1 = Q0Q3'

FF2 (Q2) changes on the next clock pulse each time both Q0=1 and Q1=1. 

J2 = K2 = Q0Q1

FF3 (Q3) changes to the opposite state on the next clock pulse each time Q0=1, Q1=1, and                     Q2=1 (state 7), or when Q0=1 and Q3=1(state 9). Thus we must have

 J3 = K3 = Q0Q1Q2 + Q0Q3

These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram above.  The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10) and causes flip-flop FF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse. Thus, the count is reset and starts over again at “0000” producing a synchronous decade counter.

We could quite easily re-arrange the additional AND gates in the above counter circuit to produce other count numbers such as a Mod-12 counter which counts 12 states from”0000″ to “1011” (0 to 11) and then repeats making them suitable for clocks, etc.

We can also build an ASYNCHRONOUS Decade Counter as shown below.

•This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10).

•On count of 10, When Both outputs QB and QD are equal to logic "1" , the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops.

•This causes all of the Q outputs to be reset back to binary "0000" on the count of 10.

• At this point,  the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10 counter.

Let's design a synchronous BCD counter. 

A BCD counter follows a sequence of ten states and returns to 0 after count of 9. These counters are also known as decade counters. This type of counter is useful in display applications in which BCD is essential for conversion to a decimal readout. Figure below demonstrates the Characteristic and Excitation table for this counter.

Figure: Characteristic and Excitation table for decade counter

There are 4 flip-flop inputs for Decade counter it implies A, B, C, D.  The subsequent state of flip-flop is given in table. JA and KA denotes flip flop input corresponding to flip-flop-A.  Please note this counter need 4-flip-flops.

From this flip flop input equations are simplified by K-Maps as displayed in figure below.  Unused minterms from 1010 through 1111 are considered as don't care conditions.

  K-maps for Decade counter

From the K-Map we can derive the Excitation Equations. 

Using  Excitation Equations, Logic circuit can be designed with 4 JK flip flops and 3 AND gates.

Figure: Logic Diagram for decade counter.