Multiplexer (MUX) is a device that allows Digital Information from several sources to be routed onto a single line of tansmission over that line to a common destination.  Basically it has several data-input lines and a single output line. There are n-data inputs, one output and m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and routes it to the output. The selection of one of the n inputs is done by the data-select inputs. Depending on the digital code applied at the selected inputs, one out of n data sources is selected and transmitted to the single output Y.  E is called the strobe or enable input which is useful for the cascading. It is generally an active low terminal, that means it will perform the required operation when it is low.  It is also known as Data Selectors.

Multiplexers come in multiple variations

Smallest MUX we have is 2 to 1 mux which has 2 input lines, 1 output line and 1 selection line. We also have 4 to 1, 8 to 1 mux and so on

• • 2 : 1 multiplexer

  • 4 : 1 multiplexer

  • 16 : 1 multiplexer

  • 32 : 1 multiplexer

Here is (the simplest Basic) 2:1 MUX

And the Simplified Boolean Expression is  Y = S'D0 + SD1

We can also build a simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND gates as shown.

The input S of this simple 2-1 line multiplexer circuit constructed from standard NAND gates acts to control which input ( D0 or D1 ) gets passed to the output at Y.

From the truth table we can see that when data select input, S is LOW (logic 0), input D0 passes its data to the output while input D1 is blocked. When data select S is HIGH (logic 1), input D1 is passed to Y while input D0 is blocked.

So by the application of either a logic “0” or a logic “1” at A we can select the appropriate input with the circuit acting a bit like a single pole double throw (SPDT) switch. 

Then in this simple example, the 2-input multiplexer connects one of two 1-bit sources to a common output, producing a 2-to-1-line multiplexer and we can confirm this in the following Boolean expression.

Y = S'D1'D0 + S'D1D0 + SD1D0'  + SD1D0

and for our 2-input multiplexer circuit above, this can be simplified too:

Y = S'D0 + SD1

NOTE:  If you analyse a MUX, you will notice that it has and is using a Decoder Circuit that controls the flow of its Input Data to the Output and it also determines how many inputs can be control in its MUX Circuit.  From the Circuit below, a 1-to-2 Decoder will contain and control a 2-to-1  Mux.

Hence , these mean that a 2-to-4 Decoder will control a 4-to-1 MUX ,  a 3-to-8 Decoder will control an 

8-to-1 MUX, and so on.

FORMING LARGER MUX

We can increase the number of data inputs to be selected further simply by following the same procedure we had done in Encoders and Decoders, hence,  larger multiplexer circuits can be implemented using smaller 2-to-1 multiplexers as their basic building blocks. So for a 4-input multiplexer we would therefore require 2 data select lines and 4-inputs represented as 2 Data Select lines  S0 and S1  (forming a 2-to-4 Decoder) to give a circuit with four inputs, D0, D1, D2, D3 as shown below.

or simply....

From the TRUTH Table we could then derived the following Boolean Function.

          Q = S1'S0'D0 + S1'S0 D1 + S1S0'D2 + S1S0D3

Then the implementation of the Boolean expression above using individual logic gates would require the use of seven individual gates consisting of AND, OR and NOT gates as shown.  Below is the Logic Circuit using AND-OR Gates for the 4-to-1 Channel MUX.

We could also implement the Logic Circuit using NAND Gates for the 4-to-1 Channel MUX, as shown below.

Below is a Mechanical Equivalent of a 4-t0-1 MUX.

In this example at any one instant in time only ONE of the four analogue switches is closed, connecting only one of the input lines D0 to D3 to the single output at Q.   As to which switch is closed depends upon the addressing input code on lines S1 and S0, so for this example to select input D2 to the output at Q, the binary input address would need to be S1 = logic “1” and S0 = logic “0”.

Then we can show the selection of the data through the multiplexer as a function of the data select bits as shown.

Multiplexer Input Line Selection

Adding more control address lines will allow the multiplexer to control more inputs but each control line configuration will connect only ONE input to the output.

Here is a Sample of an Input/Output Waveform  of a 4-to-1 MUX.

As mentioned before, we could easily design and implement a bigger MUX from smaller MUX.  Hence a 4-to-1 MUX can be built from 2-to-1 MUX.  The Procedure is quite similar in forming BIGGER Decoders and Encoders from Smaller Decoders and Encoders respectively.  Below is the configuration of combining 2-to-1 Decoders to form a 4-to-1 Decoders.

TRUTH TABLE

In a similar manner, we can build an 8-to-1 MUX from a 4-to-1 MUX as shown Below.  You will need two 4-to-1 MUX and one 2-to-1 MUX.

TRUTH TABLE 

Here a complete Illustration of 8-to-1 MUX with TRUTH Table, Logic Circuit and Block Diagram.

Boolean Implementation using MUX

To implement the Boolean function using a MUX, first, we have to determine the minterms of the Function, Then select a Suitable MUX which should have 2N  inputs to cover all the minterms of the Function.  Lastly, we just put a 0s and 1s to the inputs where a 0 signify the absence of that minterm and a 1 means the minterm corresponding to that input is present in the Function.  e.g. To implement the function F(A, B, C)= Σ (1, 2, 5, 7) using a MUX, will be needing an 8-to-1 MUX.  Then all we need is to place a 1 to all the inputs corresponding to all the minterms (1, 2, 5, 7) and the rest are 0 as shown in figure below.

                                                                                F(A, B, C)= Σ (1, 2, 5, 7)  

We can also implement the same function F(A, B, C)= Σ (1, 2, 5, 7) using a smaller MUX than 8-to-1. 

The trick is to determine the number of N variables needed in the function and then we take (N-1) variables on the selection lines and 1 variable is used for inputs of MUX.  As we have N-1 variables on selection lines we need to have  2N-1 to 1 MUX.

For the above Function  F(A, B, C)= Σ (1, 2, 5, 7),  there are 3 variables. So N = 3 and we needed a  2N-1 to 1 MUX or 4-to-1 MUX.

Just like a Decoder, a MUX can implement any Boolean function.  And there are 3 methods for implementing a circuit using a MUX.

• Algebraic Manipulation

• K-Map Method

• Numerical Method

Algebraic Manipulation

This is an approach where you can transform one boolean expression into a form so that a multiplexer can be implemented.    This can be acheived by applying Boolean Theorems and Algebra.  In using the algebraic method, the function to be considered should be minimized using the techniques covered in Minimizing Boolean Functions.   Minimising the terms and expressions can be important because this allows designers to use the least amount of components and use the most efficient type of multiplexer. 

Example 1:   Consider the function:  f(A,B,C) = A'B + BC + A'C

Expanding to standard sum of products form:

The resulting multiplexer implementation is:

Example 2:  f(A,B,C) = A'B'C' + A'B + ABC' + AC

Expanding to sum of products form:

The resulting multiplexer implementation is:

Example 3:  f(A,B,C) = A'B + B'C + BC + AB'C'

K-MAP METHOD of MUX Implementation

It can be seen that applying Boolean algebra can be awkward in order to implement multiplexers. This is because it takes a lot of practice and can be very difficult to determine the set of laws and propositions to use.  Karnaugh maps provide a simple and straight-forward method of implementing multiplexers. With the Karnaugh map Boolean expressions having up to four and even six variables can be implemented. 

EXAMPLE 1:   f(A,B,C) = A'B + BC + A'C

In the above example we could have picked any variable to be the data variable and the other two as select variables. Suppose one were to take A as the data variable. The corresponding Karnaugh map is then: 

Problems

Design multiplexer implementations for the following functions using the Karnaugh map method.

For the first problem, try using A as the data variable and B,C as the select variables. 

For the second problem, try using C as the data variable and A,B as the select variables.

For the following solutions the data variable has been suggested although any variable can be chosen as the data variable and the other two as the select variables.

Using A as the data variable and B,C as the select variables:

Using C as the data variable and A,B as the select variables.

Numerical Method Theory

When functions of many variables are being considered it is possible to cascade circuits using multiplexers of any desired size.  To simplify the theory the function is defined in binary, with a true form of a variable denoted by a 1, and conversely, a false form denoted by a 0. The system can expect to deal with variables being missing, or a don't care condition, which is denoted by a dash (-). This can be expressed clearly by the following functions of three variables, i.e. f(A,B,C). 

Essentially the method is one of factoring using the relationship 

 in which the variable allowing the maximum number of terms to be so factored is sought. That variable(s) is then used as the multiplexer data input variable.

Consider 

 Listing the two minterms we have 

 Now consider the following function.

 Note that these variables cannot be combined. 

This is because the FIRST RULE of the numerical method for two terms is that they must differ in only one digit position.

The number of variables that are true form, i.e. the number of 1's in a term, is significant and is referred to as its index.

For example: f(A, B, C, D)

0000...................Index 0 

0010, 1000.............Index 1 

1010, 0011, 1001.......Index 2 

1110, 1011.............Index 3 

1111...................Index 4

For each minterm in the function the index is found. The minterms are arranged in order of index starting with the lowest index entries. Those term-pairs with only a difference in the least weighted variable are listed. The process is repeated with a new list for those term-pairs with a difference of the next weighted variable. This continues with a further list for term-pairs, and so on.

The variable with the greatest list of pairs becomes the data input variable.

To obtain the data input values, all the minterms possible are listed in a table with the data input variable set as true and as false. Each minterm pair with its data variable value has a difference equal to the binary weight of the selected data variable. The minterms appearing in the original function are then noted.

If both terms of a pair correspond to those in the original function, the data input value is set to 1. 

If both terms of a pair do not correspond to those in the original function, the data input value is set to 0. 

For pairs with only one term corresponding to those in the original function, the data input value is set to the data variable value.

The approach resembles the tabular method of minimisation but differs in a number of respects. Instead of attempting to reduce the product terms by checking for a difference in the least weighted variable and removing this variable, and so on for the next weighted variable, each variable term is checked and these differences noted. The variable yielding the greatest number of isolated differences is the one that will provide the most efficient solution when used as the multiplexer data input variable.

Example 1:

Consider the following function to be implemented using a multiplexer:

Expanding to standard sum of products form

Arranging in index order:

To obtain the data input values, all the minterms possible are listed with the data variable set as true and as false. Each minterm pair with its data variable value has a difference equal to the binary weight of the data variable. As the data variable has been chosen to be A, which has binary weight = 4, the difference is 4. The minterms corresponding to those of the required function are now bracketed.

For both terms of a pair bracketed, set the data input value to 1. 

For both terms of a pair not bracketed, set the data input value to 0. 

For pairs with one term bracketed, set the data input value to the data variable value.

Example 2:

The function is presented in decimal form and the index found. The minterms are then compared in order to find the data variable.

All the minterms are then listed together with the data variable set as true and false in order to find the data input values.

The resulting multiplexer arrangement is:

Alternatively one could have used a 8-line to 1-line multiplexer:

Example 3:

The don't care minterm in this example is listed along with the other minterms in order to find the data variable.

When listed with all the possible minterms the don't care condition provides two possible data input values.

Using 4-line to 1-line multiplexers the logic circuit is as follows:

There are so many inputs at either 0 or 1, is it possible to economise further? (i.e. reduce the number of integrated circuit packages). For example use an 8-line to 1-line multiplexer?

From our previous list select the two longest lists, say B and E. Therefore let B,E be the data variables.

The resulting logic circuit becomes:

1 package plus 1/2 X Quad 2-input OR gate

Summary Guidelines  FOR Boolean Implementation using MUX

When a Multiplexer is used to implement a logic function, that function does not need to be minimized in the normal manner; however, a minimized function consisting of only a single literal or a single product term would be more cost-effective using a gate-lever design. Usually logic designers use truth tables to implement logic functions with Multiplexers.

Implementing  Type 0 (zero).

A type 0 MUX design requires the used of all SELECT INPUT signals  in the MUX implmenting the Boolean Function. This means, that all signals are applied to the select inputs. Also the characteristic  of the applied  signals to the data inputs are simply binary '0's and '1's, as we had illustrated before.

To illustrate again the process, the following function will be implemented using a Multiplexer:

 F(a,b,c,d)=Σ(4,5,6,7,10,14)

            Type 0 Implementation of a 16-to-1 Multiplexer design for function F

 TYPE 1, TYPE 2 and TYPE 3 Implementations.

The TYPE number N simply means this is the number of  SELECT LINES you are going to use in your implementation.  Meaning if you need to implement a Boolean Fumction that requires 16:1 MUX or 4 Select Lines, then for a TYPE 0 you need to use all the 4 Select lines.  For TYPE 1 you need to use 1 of the Select Line  as your Input Data and use the remaining 3 Select Lines  (4 less 1) or a (8:1) MUX since we have the other 1 Select Data to be used as Input Signal to  your MUX implementing the Function.  

For TYPE 2 and TYPE 3 follows the same rules, we use 2 or 3  Select Lines for our Input Data and the Remaining Select Lines determines the MUX we need for Implementation.  

TYPE 1 IMPLEMENTATION.

A type 1 MUX design requires one signal to be partitioned off. Using the same function F, 

                F(a,b,c,d)=Σ(4,5,6,7,10,14)

the truth table is now drawn and partitioned as shown below. The select inputs are independent signals a,b,c, and the data inputs are the values (the subfunctions F(d) ) in the truth table. The reduced output column in Truth Table represents the output states as function of the partitioned off input signal d. The reduced outputs in the truth table consist of a set of subfunctions of the signal that is partitioned off in the truth table.  In this case, eight subfunctions are required (3 Selects) where each subfunction is written as function of d, that is,  F(d).  

The implementation for type 1 Multiplexer design can now be shown shown using the Partitioned Truth Table.

TYPE 2 and TYPE 3  IMPLEMENTATION.

A type 2 MUX design requires 2 Select signal to be partitioned off and 

A type 3 MUX design requires 3 Select signal to be partitioned off.  Using the same function F, 

                F(a,b,c,d)=Σ(4,5,6,7,10,14)

 Truth tables (a & b) below show the partitioning for a type 2 and 3 Multiplexer design respectively.

The two signals c and d are partitioned off for a type 2 MUX design, while the three signals b, c,

and d are partitioned off for a type 3 MUX design. 

The implementation for a type 2 and type 3 MUX design are as follows.

END OF MULTIPLEXER