Registers

Registers are groups of flip-flops storing bits of information. An n-bit register is a group of n flip-flops storing n-bits of information. The basic function of a register is to hold and manipulate bits of information in a digital system and make it available to other logic elements of the computing system. Registers are synchronous circuits thus all flip-flops are controlled by a single clock. Besides storing bits of information, registers are capable of manipulating their bits of information depending on its type. 

There are four mode of operation of a shift register.

• Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or right direction under clock control.

• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form.

• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.

• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

 Serial-in to Serial-out (SISO) Shift Register

A shift register is an n-bit register with a provision for shifting its stored data by one bit position at each tick of the clock.  Figure below shows the structure of a serial-in, serial-out shift register. The serial input, Data in, specifies a new bit to be shifted into one end at each clock tick. This bit appears at the serial output, Data out, after n clock ticks, and is lost one tick later.  Thus, an n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks.

The shift register has its data  flow straight through the register and out of the other end. Since there is only one output, the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Registeror SISO.

The SISO shift register is one of the simplest of the four configurations as it has only three connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what’s the point of a SISO shift register if the output data is exactly the same as the input data. Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC’s include the 74HC595  8-bit Serial-in to Serial-out Shift Register all with 3-state outputs. 

Basic Data Movement Through A Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will remain there provided clocking of the register has stopped. In practice the input data to the register may consist of various combinations of logic “1” and “0”.   At the next Clock Tick (5th Tick) Data will be lost.

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel data output.

 If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now moved or been “shifted” one place along the register to the right as it is now at QA.

When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level “0” because the input toFFA has remained constant at logic level “0”.

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of  0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD.

Then the data has been converted from a serial data input signal to a parallel data output. 

Parallel Input Serial Output (PISO) Shift Register

• • Data bits are entered in parallel fashion.

  • The circuit shown below is a four bit parallel input serial output register.

  • Output of previous Flip Flop is connected to the input of the next one via a combinational circuit.

  • The binary input word B0,B1,B2,B3 is applied though the same combinational circuit.

  • There are two modes in which this circuit can work namely shift mode or load mode.

LOAD MODE

When the shift/load bar line is low (0), the AND gate 2,4 and 6 become active. They will pass B1,B2,B3bits to the corresponding flip-flops. On the low going edge of clock, the binary input B0,B1,B2,B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes place.

SHIFT MODE

When the shift/load bar line is low (1), the AND gate 2,4 and 6 become inactive. Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out operation take place.

BLOCK DIAGRAM

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. The data is presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections, the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required.

Bidirectional Shift Register

• • If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2.

  • Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction.

  • Such a register is called as a bi-directional register. A four bit bi-directional shift register is shown in figure below.

  • There are two serial inputs namely the serial right shift data input DR and the serial left shift data input DL along with a mode select input (M).

BLOCK DIAGRAM

OPERATION

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift register. A shift register which can shift the data in both directions is called a bi-directional shift register. Applying the same logic, a shift register which can shift the data in both directions as well as load it parallely, then it is known as a universal shift register. The shift register is capable of performing the following operation

• • Parallel loading

  • Lift shifting

  • Right shifting

The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied to D input.

BLOCK DIAGRAM

Universal Shift Register

Today, there are many high speed bi-directional “universal” type Shift Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence the name “Universal”.

These universal shift registers can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device. A commonly used universal shift register is the TTL 74LS194 as shown below.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory storage or for the delay of information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division.

Shift Register Tutorial Summary

Then to summarise a little about Shift Registers

• A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit.

• The output from each flip-Flop is connected to the D input of the flip-flop at its right.

• Shift registers hold the data in their memory which is moved or “shifted” to their required positions on each clock pulse.

• Each clock pulse shifts the contents of the register one bit position to either the left or the right.

• The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI).

• Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).

• One application of shift registers is in the conversion of data between serial and parallel, or parallel to serial.

• Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift Register with all the functions combined within a single device.

In our past lessons about Sequential Logic Circuits, we had looked at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop. This then produces another type of sequential logic circuit called a Ring Counter that are used as decade counters and dividers.