Sequential Logic Circuit

Sequential Logic Circuit

It is characterized by output values which depend on the both present and past  input/output values of the circuit. This circuit must then have some form of memory or storage elements to store and remember its past input/output values. The memory elements are devices capable of storing binary information  which defines the state of the sequential circuit.  The inputs together with the binary information of the memory determine the output state of a sequential circuit.

From the Block Diagram, we can now see that a Sequential circuit  is a function of its present inputs and past outputs. These circuits have a  memory element which stores the output of the circuit and makes it available (FEEDBACK) at the input.  The binary information stored in the memory element that is fed back into the circuit defines the state of the circuit.

There are 2 main types of Sequential Circuits. 

Synchronous and Asynchronous sequential circuit.

Synchronous Sequential Circuit is a circuit whose behavior can be defined from the knowledge of its signals at discrete instant of time. That is, its output changes are initiated by an input clock signal and in which the output change immediately upon the arrival of the  proper clock signal transition.  MOst of the Sequential circuits are Synchronous because having a Clock Signal to synchronise the outputs greatly simplifies the design of the circuit. Example for this is the FLIP Flop.

To summarise, there are four types of flip-flop:

SR Set-Reset; must not allow both inputs to be 1 simultaneously.

T Toggle type; on clocking the output either remains the same or togglesdepending if the input is 0 or 1.

JK Offering the capabilities of both the SR and T types.

D Delay-type flip-flop; upon clocking the output follows the input.

On the other hand, Asynchronous Sequential Circuit is a circuit that depends upon the order in which its input signals change and can be affected at any instant of time.  This Sequential circuit is also regarded as a  combinational circuit with memory elements which are connected to form a feedback path which caused it to be unstable.  Asynchronous Sequential circuit does not use any synchronizing clock signal. Example for this is the LATCH.

Let us analyse how a memory element or circuit can be designed and then how this memory circuit element can be incorporated into the basic building blocks for sequential circuits.

A logic circuit can maintain a constant output value by the use of feedback whereby the output is connected to the inputs in such a way to reinforce the output value.  Examine the AND Gate having its output fed-back to its input as shown below.

With the output being a 1, and fed-back to one of is input with the other inputs kept at 1, the output will remain and reinforce an output value of 1.   As long as the values of the inputs and output remain unchanged, the output will remain unchanged.  

If we change one of the input value to 0, then the output would become 0 and would remain as 0.  After this, we could not anymore force the output to become a 1.  So there is a need to revise the circuit to be able to force the output to become either a 1 or a 0.   

We need an additional input and gate to implement such circuit  (NAND Gates) as shown below.

We can redraw the circuit above as  CROSS-COUPLED NAND Gates shown below.  This is also referred to as a LATCH circuit (Set-Reset Latch or simply SR Latch).

Note that the above circuit has  ACTIVE-LO Inputs.  

Remember the NAND Gate Functionality.

Applying the NAND Truth Table to our SR Latch Circuit we will arrive at the Truth Table below.

TRUTH TABLE for SR LATCH Circuit

Here, we have used 2 NAND Gates (rather than AND Gates),  2 inputs labelled as R' (reset) and S' (set) and 2 outputs labelled as Q and Q' (Complement of Q output).  With this circuit, we now have the ability to force the output to 0, by applying a 0 to the reset input (R') while maintaining the other input S' at a value of 1, or we can force the output to 1, by applying a 0 to the set input (S'), while maintaining the other input R' at a value of 1.  Take note that the input variables are labeled with an apostrophe (Alternate for OverBar) to indicate that its is Active LO.  Once the output has been forced to a 0 or a 1, the inputs (S' or R') may change or return  to a 1 and the output still remain unchanged.  

This behavior is also known as a "LATCH".  And such digital circuit is also known as a "LATCH".  So a LATCH circuit is a Logic Circuit that maintains a given logic condition until changed by an external source.  Here is an idea of a LATCH.

We can also implement the same LATCH Circuit Design with ACTIVE-HI inputs using  NOR Gates shown below.

 Recall that a 2-input NOR Gate having one of its inputs value equal t0 0, will act like an INVERTER with respect to the other input.   Let's check.  

If one of the inputs  is at 0,  a 1 to the other input will make the output 0, and a 0 to the other input will make the output 1.   Then having one of the input at 1, will make the output 0 and remain 0 inspite of  the other input being a 1 or a 0.  Refer to its TRUTH Table above.

The same Logic INVERTER could be achieved using a NAND Gate.

Going back to our Cross-Coupled Gates, these circuits is also referred to as an SR Latch  and sometimes called an RS Latch.   Briefly describing its operation, the S-input when activated  will SET the output to 1. And activating the R-input will RESET the output to 0.

ACTIVE HI RS LATCH

ACTIVE LO RS LATCH

Block Diagram for RS Latch

The only thing we need to analyse and understand is the output state when both Q and Q' are both at the same level caused by activating the RS inputs at the same time, which should not be the case. Q and Q' should always be COMPLEMENT to each other and only one of the inputs R and S should be active at one time.  This output state takes place when both inputs S and R are both Active at the same time which is FORBIDDEN hence they are are in FORBIDDEN state.  The output in the FORBIDDEN state will not actually yield the same output value of 0 for both Q and Q' in NOR Gates RS Latch or a value of 1 for both Q and Q' in NAND RS Latch.  What really happen is that, the outputs will be both SET and RESET,  that means the output should OSCILLATE to 1 (SET) and o (RESET) a behavior that is also know as RACE CONDITION which is also referred to as UNSTABLE State.  Theoretically, thisRACE CONDITION or UNSTABLE State or OSCILLATION will take place as long as the RS inputs are both active....however, these 2 gates has delay and there are no Gates that are perfectly matched. What actually happens, is which ever Gate is Faster, then it will determine the Final output.  Hence, if the Gate having the S input is Faster, then it will SET the output to 1 (Q =1 , Q' =0). And if the Gate with R input is faster then it will RESET the output to 0 (Q =0 , Q' =1).  So in this UNSTABLE State there is no way for us to determine whether the output was SET to 1 or RESET to 0 when the FORBIDDEN state occurs. Hence iti is also referred to as INDETERMINATE State.

Here is an illustration of all the possible state of an RS Flip FLip using NOR Gates.

This UNSTABLE (INDETERMINATE) state and  RACE CONDITION occurs in both NOR and  NAND RS Latch Circuit.  

We could  add some control to our SR Input Lines in such a way to  prevent the FORBIDDEN STATE, like an  ENABLE line.  This is known as Gated SR Latch.

Gated SR latch

• The basic SR latch changes its state whenever its inputs change

• It may be desirable to add an enable signal to the basic SR latch that allows us to control when the circuit can change states

Below is the Logic Diagram of an SR Latch with Enable (EN) input.

The above circuits are also known as the GATED SR Latches. 

Latches has Transparent Outputs which  immediately change in response to input changes. The Gated RS Latches will change its outputs only if the ENABLE input is ACTIVE.  The Advantage of using this circuit is that we can prevent the occurrence of the Forbidden State. That is we can disable the GATE input whenever both SR inputs are in Active level.

 We had mentioned before that a Flip Flop is a Synchronous Sequential Circuit and that this has a SYNCHRONIZING  CLOCK SIGNAL to initiate the output changes, just like the above Enable Line of a GATED LATCH.

Actually the above circuit could be a Flip Flop if its  input could TRIGGER its output with CLOCK signals or pulses.  SO The only difference between the GATED  LATCHES and Flip Flop is in their triggering inputs or the type of Input Signal that will trigger their outputs.  Below shows that RS Flip Flops are the same as the Latches Logic Circuits and their only difference is the way they are Triggered.

For the Gated Latches, it is called LEVEL TRIGGERING.  For the Flip Flops, it is called EDGE TRIGGERING.  Their are 2 types of EDGE TRIGGERING, POSITIVE-EDGE and NEGATIVE-EDGE Triggering.    This is shown in the figures below.

Below is the TRUTH TABLE for EDGE TRIGGERING of SR FLIP FLOP

Below are samples of LEVEL TRIGGERING of SR LATCHES.

Below are samples of EDGE TRIGGERING of RS FLIP FLOP

Gated D-Latches and Flip-Flop

These circuits were designed to completely eradicate the occurrence of Forbidden or UNSTABLE state where both the Set and Reset Inputs are active at the same time.  In this circuit, the Set and Reset inputs are combined together as one and are complemented which is done by passing the same input S to an inverter and feeding it as input R, as shown below.

Gated D-Latches  

D Flip Flop

D Flip Flop Block Diagram

The important point to remember about a D-Latch and D FlipFlop is that the Q output follows the D input when enabled or triggered.  Truth Table is shown below for both the Gated D-Latch and D FlipFlop.

Below is a sample of Inputs/Output Waveform for a D-Latch.

Below are samples of Inputs/Output Waveform  for a D Flip Flop

Positive Edge Triggering

Negative Edge Triggering

A commercial D flip-flop is shown in Figure below. The D flip-flop in Figure is a TTL device

described by the manufacturers as a 7474 IC. The logic symbol for the 7474 D flip-flop shows the

regular D and CLK inputs. 

Those inputs are called the synchronous inputs, for they operate in step with the clock. The extra two inputs are the asynchronous inputs, and they operate just as in the RS flip-flop discussed previously.The asynchronous inputs are labeled preset ( PR ) and clear (CLR). The preset ( PR ) input can be activated by a LOW, as shown by the small bubble on the logic symbol. When the preset ( PR ) is activated, it sets the flip-flop. In other words, it places a 1 at the normal output (Q,. It presets Q to 1. The clear (CLR) input can be activated by a LOW, as shown by the small bubble on the logic symbol. When the clear (CLR) input to the D flip-flop is activated, the Q output is reset, or cleared to 0. The asynchronous inputs orwride the synchronous inputs on this D flip-flop.

A truth table for the 7474 D flip-flop is shown below.

 The modes of operation are given on the left and the truth table on the right. The first three lines are for asynchronous operation (preset and clear inputs). Line 1 shows the preset ( P R ) input activated with a LOW. That sets the Q output to 1. Note the X’s under the synchronous inputs (CLK and D). The X’s mean that these inputs are irrelevant because the asynchronous inputs override them. Line 2 shows the clear (CLR) input activated with a LOW. This results in output Q being reset, or cleared to 0. Line 3 shows the prohibited asynchronous input (both PR and CLR at 0). The synchronous inputs ( D and CLK) will operate when both asynchronous inputs are disabled (PR = 1, CLR = 1). Line 4 shows a 1 at the data ( D ) input and a rising clock pulse (shown with the upward arrow). The 1 at input D is transferred to output Q on the clock pulse. Line 5 shows a 0 at the data ( D ) input being transferred to output Q on the

LOW-to-HIGH clock transition.

Only the bottom two lines of the truth table  are needed if the D flip-flop does not have the asynchronous inputs. D flip-flops are widely used in data storage. Because of this use, it is sometimes also called a data flip-flop.

J-K Flip-Flop

 The most widely used and versatile FlipFlop.  The functionality of the J-K FLip FLop is identical to that of the SR Flip Flop in the SET, RESET and NO CHANGE conditions of operation.   In addition, J-K flip flop provides TOGGLE operation.  The J-K flip flop is a refinement of RS flip flop so that the UNSTABLE or indeterminate state of the RS type is made STABLE or defined in J-K flip flop.  (Note, J is for Set and K is for Reset) .  In J-K, when both J, K inputs are Active, the outputs Q, Q' will simply change to its complements in other word, it TOGGLES.  Below is the Logic Circuit and Symbol of a J-K Flip Flop.

The output Q is ANDed with K and CP inputs so that the flip flop is RESET or cleared if Q was previously 1 during a Clock Pulse.  Similarly, output Q' is ANDed with J and CP inputs so that the flip flop is SET if Q' was previously 1 at a Clock Pulse.  The TRUTH TABLE is shown below.

Q here is the PRESENT Output which is fed back to the  input and Q(t+1) is the next  Output at the Clock Pulse.  Notice that when the inputs J,K are both 0, the outputs remain the same and when both are 1, the outputs will TOGGLE or switch to its Complements.

Here is another version of the TRUTH TABLE for JK flip flop.

The modes of operation are given on the left and the truth table is on the right. Line 1 of the truth table shows the hold, or disabled, condition. Note that both data inputs ( J and K ) are LOW. The reset, or clear, condition of the flip-flop is shown in line 2 of the truth table. When J = 0 and K = 1 and a clock pulse arrives at the CLK input, the flip-flop is reset ( Q = 0). Line 3 shows the set condition of the JK flip-flop. When J = 1, K = 0, and a clock pulse is present, output Q is set to 1. Line 4 illustrates a very useful condition of the JK flip-flop that is called the toggle position. When both inputs J and K are HIGH, the output will go to the opposite state when a pulse arrives at the CLK input. With repeated clock pulses, the Q output might go LOW, HIGH, LOW, HIGH, LOW, and so forth. This LOW-HIGH-LOW-HIGH idea is called toggling. The term “toggling” comes from the ON-OFF nature of a toggle switch.

The JK is considered the universal flip-flop. Figure (a) below shows how a JK flip-flop and an inverter would be wired to form a D flip-flop. Note the single D input at the far left and the clock input (Negative Edge Trigger). This wired D flip-flop would trigger on the HIGH-to-LOW transition of the clock pulse, as shown by the bubble at the CLK input.  

A useful toggle flip-flop (T-type flip-flop) is shown wired in Figure (b).  A JK flip-flop is shown being used in its toggle mode. Note that the J and K inputs are simply tied to a HIGH, and the clock is fed into the CLK input. As the repeated clock pulses feed into the CLK input, the outputs will simply toggle.   The toggle operation is widely used in sequential logic circuits. Because of its wide use, a special symbol is sometimes used for the toggle (T-type) flip-flop. Figure (c) shows the logic symbol for the toggle flip-flop. The single input (labeled T ) is the clock input. The Customary Q and outputs are shown on the right of the symbol. The T flip-flop has only the toggle mode of operation.

One commercial JK flip-flop is detailed in Figure below. This is described by the manufacturer as a 7476 TTL dual JKflip-flop. A pin diagram of the 7476 IC is reproduced in Figure. Note that the IC contains two separate JK flip-flops.  Each flip-flop has asynchronous preset (PR) and clear  (CLR) inputs. The synchronous inputs are shown as J , K , and CLK (.clock).  The customary normal ( Q ) and  complementary (0) outputs are available. Pins 5 and 13 are the +5-V (V,,) and GND power connections on this IC.

A truth table for the 7476 JK flip-flop is shown in Figure below. The top three lines detail the operation of the asynchronous inputs preset (PR ) and clear (CLR). Line 3 of the truth table shows the prohibited state of the asynchronous inputs. Lines 4 through 7 detail the conditions of the synchronous inputs for the hold, reset, set, and toggle modes of the 7476 JK flip-flop.

Most commercial JK flip-flops have asynchronous input features (such as PR and CLR). Most JK

flip-flops are pulse-triggered devices like the 7476 IC, but they can also be purchased as edge triggered

units.

T Flip FLop

This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together and thus are also called a single input J-K flip flop. When clock pulse is given to the flip flop, the output begins to toggle.  This is also referred to as TOGGLE  Flip Flop or simply T Flip Flop.  

Characteristic Tables and  Characteristic Equations

The characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form. This Table is also called the FUNCTIONAL TRUTH TABLE.

The characteristic tables of three types of flip-flops are presented in Table below, 

They define the next state (i.e., the state that results from a clock transition) as a function of the inputs and the present state, Q(t) refers to the present state (i.e., the state present prior to the application of a clack edge).  Q( t+1 ) is the next state one clock period later. Note that the clock edge input is not included in the characteristic table, but is implied to occur between times t and t+1. Thus, Q(t) denotes the state of the flip-flop immediately before the clock edge trigger, and Q(t+1) denotes the state that results from the clock transition.

The characteristic table for the JK flip-flop is as follows:

1)  when inputs J and K are both equal to 0. table shows that the next state is equal to the present state.  This condition can be expressed as Q(t+1) = Q(t), indicating that the clock produces NO CHANGE of state  or (HOLD).  

2) When J = 0 and K = 1,  tbe clock RESETs the  flipflop and Q(t+1) = 0. 

3) When  J = 1 and K = 0,  tbe clock SETs the  flipflop and Q(t+1) = 1.

4) When both J and K are equal to 1, the next state or output changes to the complement of the current state or  (outputs TOGGLE), a transition that can be expressed as Q(t+1) = Q'(t).

Now we an expand our Functional Truth Table by including the previous output Q(t) as one of the input.

Characteristic Equation

From the Characteristic Table we can derived the corresponding Characteristic Equationof the JK flip flop.  Characteristic Equation  is the Algebraic expression of the Logical Properties of a Sequential Circuit. Using K-Map we get the following;

   Q(t+1) = J.Q'(t) + K'.Q(t)

We can do likewise with the SR flip flop.  First we get its Characteristic or Functional Truth Table as shown below.

Then using K-Map.

We get the Characteristic Equation of an  Active-Hi RS flip flop. 

 Q(t+1) = S + R'.Q(t)

We can also get the Characteristic Equations for the Other flip flops.

Specify next state as a function of its current state and inputs

• Q(t) = current state

• Q(t+1) = next state

Therefore 

• SR latch:        Q(t+1) = S + R’Q(t)

• D flip-flop:     Q(t+1) = D

• JK flip-flop:   Q(t+1) = JQ’(t)+K’Q(t)

• T flip-flop:     Q(t+1) = T⊕Q(t)= TQ’(t)+T’Q(t)

Flip-flops are the fundamental building blocks of sequential logic circuits. Therefore, IC manufacturers

produce a variety of flip-flops using both the TTL and CMOS technologies. Typical TTL flip-flops are the 7476 JK flip-flop with preset and clear, 7474 dual positive-edge-triggered D flip-flop with preset and clear, and the 7475 4-bit bistable latch. Typical CMOS flip-flops include the 4724 8-bit addressable latch, 40175 quad D flip-flop, and the 74C76 JK flip-flop with preset and clear.

 End of Flip Flop