seatwork-004

1) Design the 3 Bits Up/down counter (Gray code sequence) Using JK FlipFlops.  Refer to the State Diagram Below.

From the State Diagram, It has an Input Y which direct the flow of Sequence as either UP (forward) or DOWN (backward), when its Value is 1 (Y=1) or 0 (Y=0) respectivelly.

In your Implementations, show your complete solutions and Derive the Following.

• State Table and Excitation Table

• K-MAPS  to derive the Excitation Equations 

• Using your Excitation Equations, Derive or Implement the Logic Circuit for the  3 Bits Up/down counter (Gray code sequence)

2) Design a Frequency Divider which is  Divide-by-6 Counter or MODULO-6 counter (6 STATE outputs)     i.e.  000 - 001 - 010 - 011 - 100 - 101.  

The circuit should be SYNCHRONOUS and with JK Flip Flops.

In your Implementations, show your complete solutions and Derive the Following.

• State Table and Excitation Table

• K-MAPS  to derive the Excitation Equations 

• Using your Excitation Equations, Derive or Implement the Logic Circuit 

• Draw the TIMING DIAGRAM Waveforms for a complete Cycle (Modulo-6).

• Revise and Transform your MODULO-6 counter to a MODULO-12 Counter, by using or cascading a Modulo-2 Counter to Modulo-6 counter.

• Draw the TIMING DIAGRAM Waveforms for a complete Cycle of  the Modulo-12.

3)   Here is a Bit Asynchronous Binary  RIPPLE Counter.  It has  a 4-bit asynchronous binary counter and its timing diagram for one cycle. It works exactly the same way as a 2-bit or 3 bit asynchronous binary counter mentioned above, except it has 16 states due to the fourth flip-flop.

We have learned that we can easily tranform a RIPPLE COUNTER to a MODULO-n counter by using its CLR input to CLEAR (RESET) the FlipFlops after reaching its n-STATE of the Modulo-n Counter to force the circuit to Recycle on the nect Clock Pulse. 

Let us revised and transform the 4-bit Ripple Counter to a Modulo-10 counter (Q3Q2Q1Q0).  So that means it should cycle from 0000 to 1001, and that after reaching its 10-STATE or 1001 , the circuit should be RESET at 1010 at the next Clock Pulse.  This could easily be done using a NAND Gate with inputs from Q3 and Q1 as shown below.

NOTE: That the NAND Gate will be Triggered by the Outputs Q3 and Q1 of outputs Q3Q2Q1Q0

where Q3 and Q1 will be both high when the output is at 1010, the value where we want our circuit to RESET all its output to 0000 and Start the Cycle again.

A) Design a  MODULO-11 counter using the same Procedure as above. 

• Draw the TIMING DIAGRAM Waveforms for a complete Cycle (Modulo-11).

B) Design a  MODULO-13 counter using the same Procedure as above. 

• Draw the TIMING DIAGRAM Waveforms for a complete Cycle (Modulo-13).