Programmable Logic Device or PLD

Programmable Logic Device or PLD 

is an integrated circuit with internal logic gates connected through electronic path that behave similarly to fuses. In the original state of the device, all the fuses are intact.   Programming the device involves blowing those fuses along the paths that must be removed in order to obtain the particular configuration of the desired logic function.

Here is a Schematic Diagram of a PLD showing its Programmable Links.

Here is a simplified version of  a diagram for PLD with all the fuses intact.

Here is a Programmed PLD implementing F = A'B + AB'

Here is another IMPLEMENTATION with Simplified Diagram.

Here is an implementation of Boolean Functions (XOR, NAND, NOR) using PLDs.

PLDs - PROM, PAL, PLA

There are three major types of combinational PLDs differing in the placement of the programmable connections in the AND-OR array.  Refer to the Figures below.

(a) The PROM or Programmable Read-Only-Memory has a fixed AND  constructed as a decoder and a programmable OR array. The programmable OR gates implement the Boolean functions in sum-of-minterms  form. 

(b) The PAL or Programmable Array Logic has a programmable AND array and a fixed OR array. The AND gates are programmed to provide the product terms for the Boolean functions, which are logically summmed in each OR gate.

(c) The most flexible PLD is the PLA or Programmable Logic Array, in which both the AND and OR arrays can be programmed. The product terms in the AND array may be shared by any OR gate to provide the required  sum-of-products implementation.

Memory

A memory unit is a device to which binary information is transferred for storage and from which information is retrieved when needed  for processing. There are two types of memory that are used in digital systems: Random-Access memory (RAM) and Read-Only memory (ROM). ROM can only perfom the read operation (retrieving / accessing), while RAM can perform both the read/write read operations.  ROM is a non-volatile memory and RAM is a volatile memory.

Volatile memory is a type of memory storage whose data contents are erased when the system's power is turned off or interrupted.

Non-Volatile memory is a type of memory storage whose data contents are retained even when the system's power is turned off or interrupted.

This means that in ROM,  binary information is already stored inside this device and they can be retrieved or read at any time, but that information cannot be altered by writing. ROM is a Programmable logic Device (PLD). The binary information that is stored within such a device is specified in some fashion and then embedded within the hardware in a process referred to as "programming the device". Tbe word "programming" here refers to a hardware programming procedure which specifies the bits that are inserted into the hardware configuration of the device. 

This programmable ROM is also often referred to as PROM is a combinational PLD - an integrated circuit with programmable gates divided into an AND array and an OR array  to provide an AND-OR sum-of-product implementation, 

A PLD is an integrated circuit with internal logic gates connected through electronic path that behave similarly to fuses. In the original state of the device, all the fuses are intact.   Programming the device involves blowing those fuses along the paths that must be removed in order to obtain the particular configuration of the desired logic function.

A typical PLD may have hundreds to millions of gates interconnected through hundreds to thousands

of internal paths. In order to show the internal logic diagram of such a device in a concise form, it is necessary to employ a special gate symbology applicable to array logic.  

A ROM is essentially a memory device in which permanent binary information is stored. The

binary information must be specified by the designer and is then embedded in the unit to form

the required interconnectionpattern. Once the pattern is established, it stays within the unit even

when power is turned off and on repeatedly.

A block diagram of a ROM consisting of k inputs and n output lines (2k x n) is shown in Figure below. 

Each bit combination of the input variables is called an ADDRESS and each bit combination that comes out of the output is called a WORD.   Hence, The inputs provide the address for the memory, and the outputs give the data bits of the stored word that is selected by the address. The number of words in a ROM is determined from the fact that k address input lines are needed to specify 2k words.    An address is essentially a binary number that denotes to one of the minterms of k input variables.  Hence the number of distinct addresses possible with k input variables is 2k.  An output word can be selected by a unique ADDRESS, since there are 2k distinct address ina ROM, then there are 2k words that could be stored in the unit.   The word available on the output lines at any given time depends on the value of the ADDRESS lines. The number of bits per word is equal to the number of output lines n.  A ROM is characterized by the number of WORDS  or disticnt ADDRESS 2k and the number of bits per word n or (2k x n) ROM.

A more detailed block diagram of a ROM consisting of n inputs and m output lines or (2n x m) ROM is shown in Figure below.

The n input address lines of the Decoder portion of the ROM will produce 2n Memory Selection lines or word lines or 2n Memory Locations (Horizontal lines coming out of the Decoder).  The output Data is the m output lines coming out vertically from the Memory Array.  Each row of the Memory Array is often referred to as "word".  The "word size" is called the "bit width" (the number of bits in a word or the bit-size of the memory data), which is m the number of output lines coming out vertically from the Memory Array.  A word in the memory array could be selected by a "Memory ADDRESS line"  which is a line coming from one of the 2n word lines of the Decoder.  A  single Memory ADDRESS is produced by the n address lines of the Decoder.  Since there are 2nMemory Address produced by n Address Lines, then there will be 2n words of m-bit size accessible in the Memory Array.  We could also say that the ROM has a total number of bits equal to (2n x m) bits. 

For example, a  2048-bit ROM having a 4-bit data output will be organized as 512 words of 4 bits each.  This means that the ROM has 9 address lines and 4 output lines. and this will provide a 512 word lines or Address lines to access any of the 512 words of 4 bits each.  This makes the total number of bits in this ROM as equal to 512 x 4 bits or 2048 bits. We can also call this a 512 x 4 ROM.

Let us Consider, for example, a 32 X 8 ROM. The unit consists of 32 words of 8 bits each. There

are five input lines that form the binary numbers from 0 through 31 for the address. Figure below 

shows the internal logic construction of this ROM. The five inputs are decoded into 32 distinct

outputs by means of a 5 X 32 decoder. Each output of the decoder represents a memory address.

The 32 outputs of the decoder are connected to each of the eight OR gates. The diagram shows the array logic convention used in complex circuits.  Each OR gate must be considered as having 32 inputs. Each output of the decoder is connected to one of the inputs of each OR gate.  Since each OR gate has 32 input connections and there are 8 OR gates, the ROM contains 32 X 8 = 256 internal connections, which are programmable. In general, a 2k X n ROM will have an internal k X 2k decoder and n OR gates. Each OR gate has 2k inputs, which are connected to each of the outputs of the decoder.

The 256 intersections in the above Figure are progmmable. A programmable connection between  two lines is logically equivalent to a switch that can be altered to be either closed (meaning that  the two lines are connected) or open (meaning that the two lines arc disconnected). The programmable  intersection between two lines is sometimes called a crosspoint. Various physical devices are used to implement crosspoint switches. One of the simplest technologies employs a fuse that normally connects the two points, but is openned or "blown" by the application of a high-voltage pulse into the fuse.

BOOLEAN FUNCTION IMPLEMENTATION in ROM

From the Logic circuit above, we had learned that a decoder will generate all the possible mintermsfor a k-inputs decoder.  We also learned that any Boolean Function can be expressed in sum-of-product terms or sum-of-minterms.  So by creating a link to all the minterms included in the Boolean Function, then we can make each of the ROM outputs to implement the Boolean Function in the combinational circuit.

Let us consider the following Boolean Functions for implemantation.  

F1(A,B,C,D) = Σ(1,2,4,7)

F2(A,B,C,D) = Σ(0,3,5,6)

F3(A,B,C,D) = Σ(1,3,5,7)

F4(A,B,C,D) = Σ(2,3,4,5)

Let us express each Function in terms of the variables (A,B,C,D)

F1 = A'B'C + A'BC' + AB'C' + ABC

F2 = A'B'C' + A'BC + AB'C + ABC'

F3 = A'B'C + A'BC + AB'C + ABC

F4 = A'BC' + A'BC + AB'C' + AB'C

Let us first implement the Boolean Functions using a 3:8 Decoder.  This is easily done by just taking all the summations of all the minterms in the Functions as shown below.

The ROM Implementation is exactly the same as it contain the same elements for the Decoder implementation.  For the ROM implementation, all we need is to "program"  it.    Programming the ROM device involves removing the linkks or paths that must be removed in order to obtain the particular configuration of the desired logic function.  To implement the Functions above we need a

3 x 4 ROM .  Using the special Gate Symbology we have the ROM implementation below.

Another example of Boolean Implementation in ROM using the TRUTH TABLE given  below.

Every Zero (0) listed in the TRUTH TABLE specifies the absence of a connection, and every ONE (1) listed specifies a path that is obtained by a connection.  For example, the table specifies the eight-bit word 101 10010 for permanent storage a! address 3.  The four O's in the word are programmed by blowing the fuse or connecting links between output 3 of the decoder and the inputs ofthe OR gates associated with outputs D6, D3, D2, and Do.  The four 1's in the word are marked with a X to denote a temporary connection, in place of a dot used far a permanent connection in logic diagrams. 

When the input (I4,I3,I2,I1,I0) of ROM  is 00011 , all the outputs of the decoder are ZERO (0) except for output 3, which is at logic 1.  The HI output logic signal at output 3 of the Decoder will Activate the output OR Gates of D7, D5, D4 & D1 while the other outputs are at LO or are disabled.

The result is that the stored word 1011 0010 is applied to the eight data outputs, which corresponds to the TRUTH TABLE at input  (I4,I3,I2,I1,I0) of ROM  at 00011 or ACTIVE Output 3.

DIFFERENT TYPES OF ROM

There are different types of ROM and each has its own different ways of HardWare (H/W) programming. 

The first is the CUSTOM-MADE ROM which is created by the Manufacturer according to the required SPECIFICATIONS of a USER or CUSTOMER.  The PROGRAMMING is done by the MANUFACTURER during the FABRICATION PROCESS of the UNIT which is called MASK-PROGRAMMING.

The second type is the programmable read-only memory, or PROM.  At first When ordered, PROM units contain all the fuses or connecting links intact, giving all 1's in the bits of the stored words. The fuses in the PROM are blown by the application of a high-voltage pulse to the device through a special pin. A blown fuse defines a binary ZERO (0) state and an intact fuse gives a binary ONE (1) state. This procedure allows the user to program the PROM to implement the desired TRUTH TABLE.  The Hardware Prograaming is done thru the used of a special device called PROM PROGRAMMER device.  Take note, the hardware procedure for programming ROMs or PROMs is irreversible and once programmed, the fixed pattern is permanent and cannot be altered.  Once a bit pattern has been established, the unit must be discarded if there is a need of any revisions or to change any of the bit pattern as it requires re-Programming the ROM. As mentioned before, programming ROMs or PROMs is irreversible and once programmed, the fixed pattern is permanent and cannot be altered.  Revisions will require a NEW set of ROM to be Programmed.

A third type of ROM is the erasable PROM, or EPROM, which can be restructured to the initial state even though it has been programmed previously. When the EPROM is placed under an ultraviolet light

for a gven length of time, the shortwave radiation discharges the internal floating gates thereby wiping away or erasing all information previously stored in the EPROM.  After erasure, the EPROM is back to its initial state and can be reprogrammed to a new set of values.

The fourth type of ROM is the electrically erasable PROM (EEPROM or E2PROM). This device is like the EPROM, except that the previously programmed connections can be erased with an electrical signal instead of ultraviolet light. The advantage is that the device can be erased without removing it from its socket. 

The Flash memory devices are similar to EEPROMs, but have additional built-in circuitry to selectively program and erase the device in-circuit, without the need for a special programmer, allowing simultaneous erasing of blocks of memory, for example, of size 16 Kbytes to 64 Kbytes. Like EEPROMs,

flash memories are subject to fatigue, typically having about 105 block erase cycles.