PAL, PLA, GAL

Programmable Logic Device -  PROM, PAL, PLA

There are three major types of combinational PLDs differing in the placement of the programmable connections in the AND-OR array.  Refer to the Figures below.

(a) The PROM has a fixed AND may constructed as a decoder and a programmable OR array, The programmable OR gates implement the Boolean functions in sum-of-mintems form. 

(b) The PAL has a programmable AND array and a fixed OR array. The AND gates are programmed to provide the product terms for the Boolean functions, which are logically summmed in each OR gate.

(c) The most flexible PLD is the PLA, in which both the AND and OR arrays can be programmed. The product terms in the AND array may be shared by any OR gate to provide the required 

sum-of-products implementation.

PAL was developed to overcome certain disadvantages of the PLA, such as longer delays due to the additional of fusible links that result from using the 2 programmable arras and more circuit complexity.  The PAL consists of a programmable array of AND gates connected to a fixed array of OR gates and it is a one-time programmable logic device.  The block diagram of PAL is shown below;

The structure allows any Sum-Of-Products (SOP) logic expression with a specific number of Variables to be implemented.  The basic structure of a PAL shown below has 2 input variables and 1 output, although true PALs have more many more inputs and outputs.  Programmable array is essentially a GRID of conductors forming rows and columns with a fusible link at each CROSS-POINT.  Each fuse at the CROSS-POINT is called a CELL and is the programmable element in PAL.

The implementation of SUM-of-PRODUCTS Expression is done by breaking the CELL or blowing out of the FUSIBLE LINK  between a row and column where a connection is not needed and keeping intact all those CELLS where the connection between a row and column is required, which is carried out during the PROGRAMMING PROCESS.

As an example, let us implement the Function X = AB + AB' + A'B'.  Programming a PAL to implement the Function is shown below.

As you can see, the FUSES are blown out or OPENNED to all the CROSS-POINTS where connection is not needed or where the variable or its complement is not required to the inputs of the AND Gates.  While the Fusible Links are kept intact to connect all the desired variables and their complements to the inputs of the AND Gates.  From the above circuit, there are 3 AND Gates and the top most AND Gate has  A and B as its inputs, the middle AND Gate has A and B' and the last AND Gate is A'B'.  And the final output at the OR Gate is the Summation od all these Product Terms which will give us the Function X = AB + AB' + A'B.

The above diagram can be simplified using the symbology for the array logic as shown below.

Let us Program a PAL to implement the Following Function X = AB'C + A'BC' + A'B' + AC.

Here is a real PAL circuit fabricated by Advanced Micro Devices, which is name as  PAL16L8.

The numbers stand for the number of inputs and outputs. There are 16 inputs and 8 outputs. The L stands for ACTIVE-LO outputs.

PLA consists of a programmable array of AND gates and programmable array of OR gates.

The PLA was developed to overcome some of the limitations of the PROM.  PLA is also called the FPLA (Field Programmable Logic Array) because it is the user in the field who programs it and not the manufacturer.  Below is the block diagram of  a PLA.

Below is the Logic Circuit of a PLA, with all Fuses still intact (not yet programmed).

Here is a simplified version of UN-USED PLA using the symbology for logic array.

Now, let us design a Function Generator of 3 inputs.  The circuit should should implement the Logic Functions AND, OR, NAND, NOR, XOR and XNOR.

The PLA implementation of the collection of Functions is shown below.

Take note, that the following terms ABC and A'B'C' are seen and shared in more than 1 output Functions.  F1 (AND) and F5 (XOR) share the term ABC, while F4 (NOR) and  F6(XNOR) share the term A'B'C'.  This manner of implementation where a Product Term could be shared to more than one Function is the KEY DIFFERENCE between a PAL and PLA.  This also means that PLAs can implememt a much more complex collection of Functions than a PAL, in cases there are huge number of product terms being shared,

For our next example,  Let us implement some simple Boolean Function using a PLA.  Let us have the following functions.

f1 = AB'C

f2 = AC + BC

f3 = A'B' + AC'D' + AB'C

Using a PLA we have the following to generate all of the above functions.

Let us now implement the Logic Circuit for BCD-to-7-Segments Decoder using a PLA.

Using the Truth Table

PLA implementation is shown below.

For our last example, let us implement a FULL-ADDER using a PLA.

GENERIC ARRAY LOGIC (GAL)

The GAL is similar to  PAL, as it has PROGRAMMABLE AND ARRAY  connected to a FIXED OR ARRAY. 

 The difference between a GAL and PAL is that GAL has PROGRAMMABLE OUTPUT LOGIC and it is RE-PROGRAMMABLE, hence GAL can be re-used over and over again.  It uses the E2CMOS (Electrically Erasable CMOS) technology, this make it re-programmabl and re-usable.

The basic structure of a GAL is illustrated in Figure below.  It has 2 input variables and 1 output although most GALs have many inputs and many outputs.  The re-programmable array is essentially a grid of conductors forming rows and columns with an E2CMOS cell at each CROSS-POINT rather than the usual FUSES in PROM, PAL and PLA.

To program the GAL, we only need to turn ON or OFF (to PROGRAM) the E2CMOS cell, where the ON cells make connection and the OFF cell make a disconnection. The programmed state of a GAL could be retain for 20 years.  

Here is a simple Boolean implementation of a GAL.

Here is a another example with programmable output.

OLMC - Output Logic Macro Cells - this is the Programmable Output part of GAL which contain the OR Gates Array and Programmable Logic.  

Here is another Block Diagram of GAL with Programmable Output (OLMC).

Here is a typical Logic Circuit of OLMC (Output Logic Macro Cells).

END of PLD