Example of Logic Design & a Two-Phase Clock

A Sliver-Free, Two-Phase Logic Clock To Overcome Clock Skew In State Machines And Counters

Nature of article: five page, illustrated technical report

Author: John Engelbrecht Augusta Solder and Circuits

Date: July 11, 2011

Expertise level: medium

Written for: people learning logic design

Particular to logic family: flip flops triggered on rising clock, with Qs changing a propagation delay later. Most applicable to chips having global clock such as complex programmable logic devices (CPLD) Atmel ATF1504AS, $6. Not needed by old, TTL-style, master-slave flip flops.

1) A logic family that is not bothered by clock skew: TTL flip flop master-slave such as 7476. Reference

But this arrangement gives slower performance than modern flip flops which are rising-clock triggered, where Qs respond within several nanoseconds (ns) of the clock.

2) In contrast, modern logic implementing state machines (generally two to six D flip flops with Qs feeding back into Ds to establish the next state, all clocked in common) is susceptible to clock skew. Clock skew is where some flip flops receive their clock 3 to 10 ns late and experience undesired transitions on D inputs as the clock rises. The undesired D inputs come from flip flops that got an earlier clock. This messes up the operation of the state machine or counter and is hard to diagnose.

This can be caused by the following.

a)Slowly rising clock, or the various flip flops have clock thresholds varying by tenths of a volt.

b)Different conductor lengths for the clock, where it takes about .7 nanosecond per foot for the clock signal to travel.

c)Multiple clock transitions caused by ground bounce, supply ringing, reflections on clock wiring, or logic slivers at the source of the clock.

d)Clock distribution on a chip by other than global clock network.

e)When a large synchronous counter gets too large, like four decades, and CPLD fitting software can't keep clock distribution adequately synchronized.

f)Wikipedia classifies the problem into hold violation and setup violation.

The problem of clock skew is one of a host of digital problems. Though digital design is superficially a simple matter of ones and zeros, lacking the complexity of analog design, in reality there are many messy problems in digital. Digital designers who know analog and Electromagnetic Compatibility are the best digital designers.

3) Clock skew is readily overcome by a well-known, two-phase clock, simulating the master-slave system, at the expense of double the flip flop count. (The Greek Phi symbol in the figures is pronounced as Phase.)

The following figure introduces a Strobe signal that will be explained shortly.

4) There may be other ways of managing clock skew, this article is not a comprehensive survey. Logic development software offers timing simulation that can predict skew problems.

5) An example of a two-phase clocking system.

Referencing from above and repeated here, a circuit provides a "strobe" signal that can be ANDed with any signal developed by AND/ORing of the state bits, to insure that the AND/ORs are using stable, sliver-free, state-machine bits. STROBE is high duty cycle, 14/16=87%.

Note that the state bits (the ones from the second rank of Ds) transition at t8, midway in the down time of STROBE, well away from when STROBE is high.

Paragraph Six shows the development of the logic for these waveforms.

6) Logic for Paragraph Five's two-phase clock and STROBE

This can be done as master-slave simulations (requires eight flip flops), but is shown here with four flip flops using a global clock. This is a small, stable fit in an Atmel CPLD, as long as the 16x clock has sharp transitions and there is a good ground plane. This logic development is not a tutorial, all the steps are not explained.

6a) The four bits of the sixteen-state machine are E F G H. The state flow is shown below. It is a Gray code (at each transition, one and only one bit changes), which gives reduced slivering.

6b) Once STROBE goes high, transitions on the P-terms that make up STROBE are covered by other, TRUE P-terms to insure no slivering. There is one exception, the rise of E, where E'F is going away, as follows.

6c) The sliver can be covered by the orange P-term in the Strobe equation above. The reason that a Gray code allowed a sliver is that, apparently, equations descending from Gray bits can have slivers, but additoinal P-terms, such as the orange term, can cover the slivers.

7) An electronic instrument, a transistor curve tracer, as described here, needs the two-phase clock of Paragraph Six. This instrument handles high-power transistors, uses up to 10 amps and 169 volts, employs 120VAC relays with arcing contacts, and generates a lot of noise. The instrument applies various base currents to a transistor and shows the resulting currents and voltages. It has many controls to handle both polarities of regular transistors, FETs, and all the diode types. Due to the high voltage, special attention must be paid to safety so that no one is injured by the finished product.

These curves show a lot of things. You can get Beta (current gain) and saturation voltage. If you crank up the Vce, you can see the transistor's breakdown voltage.

7a) The curve tracer uses master-slave-style flip flops, and they need the two-phase clock. These flip flops are therefore tolerant of noise and slow clock transitions. These problems could be exacerbated if the logic has to be split between two CPLD chips, for instrument control and to send a PC the data on an RS-232 serial port.

7b) Some curve tracer signals are one-shot triggered from the state machine and must use STROBE to prevent false triggering.

7c) An eleven-state state machine to control the instrument

(This is a summary, training on how to do all of this is a college-level subject.) Since two-phase clocking is used, there is no need for Gray code in the state transitions. The state transition diagram following allows the flip-flop D input equations to be derived so that the CPLD development system can be used to program a chip. Think of the state transition diagram as being a flow chart organized to show the four bits that are four flip flops.

The green state, ABCD=0000, is the state whenever the safety cover over the transistor is open. You stay in this state until the cover closes, then on the next clock you go to 0001 in case the capacitor hasn't finished charging.

Every used state (there are 11 of them) has at least one entry arrow and at least one exit arrow. Each transition shows a condition except for transitions that happen unconditionally, such as from 1001 to 1010 to 1011 to 1100 to 1101.

The pink state is where data is taken on the transistor and sent to a PC, where a custon-written program graphs the data. The pink state stands for a subsidiary state machine that operates four sample/hold circuits that feed into an analog-to-digital converter that feeds onto the serial port of the PC. The pink state is maintained until the capacitor discharges, at which time a new base-current step (or gate voltage step for a FET) will be applied and a new curve sampled.

The state diagram is gone though eight times (000 to 111 on the step counter, which is itself another state machine), at which time the family of eight curves has been assembled on the PC so you can evaluate the transistor for use in your next project.

A word about the clock speed for this instrument: about 3ms per state is a good speed, there are relay operations and capacitor charge/discharge that are slow. The clock generator runs at 16x speed, 1/3ms x 16 = 5300Hz.

7d) Karnaugh map showing transitions

7e) Equations of the four flip flops, derived from the state transition diagram above, not showing the intermediate step of the four Karnaugh maps, one for each flip flop.

With these equations in hand, you are ready to get on the development system for a programmable logic chip and get your chip programmed. Since this is a complex, interesting sytem, it is prudent to simulate it somehow and see if there are errors. I spent three hours on Excel and found two things that needed tending to.

8) Conclusion

A two-phase clocking scheme is presented. It is a good clock for noisy systems (as presented in Paragraph Seven), and it overcomes clock skew problems.