Embedded Files
September 2012
Three years of Atmel CPLD experience leads to some recommendations.
1) I recommend spending $100 for the ATF15xx-DK3 development kit, photo on the one-up web page. If you search Internet for Atmel Xilinx CPLD PLCC socket you find http://fixunix.com/cp-m/161-atmel-xilinx-cplds.html which, for me, is the right level of DIY.
2) Atmel CPLD Reference Designs Prove Logic Doubling(TM) Works White Paper March 1, 2001 is a medium-level discussion through the $8 ATF15xx family of complex programmable logic devices (CPLD). Search Internet for the .pdf . More learning is in the spec sheet for, for instance, ATF1504AS.
3) CPLD can be understood only if you know about simple PLDs which have been around for 25 years. SPLD do combinatorial logic (gates) and sequential logic (flip flops, registers, state machines) at the $2 to $15 range in lower-pin-count packages, including .3"-wide DIPs. But to program them, you need a $1000 programmer. The advantage of CPLDs that are ISP, in-system programmable through a JTAG 10-pin header, is that you leave the device in your circuit when you reprogram it, the programming hardware is a small circuit built into a cable (like a parallel port cable), and the software is free or low cost.
4) Continuing from 3), if your DIY PC board etching capability is like mine (MG Chemicals 600 series, positive photo process, green coating, OK down to .013" lines and spaces), you have a choice between PLCC socket with 44 or 84 holes drilled through your board (eats up drill bits, lots of work, but replaceable IC if you shock it or forget to enable JTAG) or solder the PLCC or gull-wing-pin TQFP to your board. In Oct 2012, I will try soldering on single-CPLD boards which plug together to make a bigger system, where you lose a smaller amount of work if one IC solders wrong. IC pins that are no-connect don't have to be soldered at all.
5) All PLDs that are the -15 speed grade (15 ns) or faster put you in the RF regime. Simple gating is no problem, but flip flops with clocks can get false triggering, double clocks, reflections on wires, and other EMC (electromagnetic compatibility) problems. There are general ways to handle these problems (supply decoupling caps, compact layouts, multiple grounds between boards, ground plane on PCB, sharp clock edge rather than slow clock edge, 50 or 100 ohm termination of longer wires at the expense of high-power drivers, coax, etc.) but mastering these high-speed problems is an arcane branch of electrical engineering, EMC. The awfulest thing about logic races and double clocking is that they may not go away when you dial down the clock frequency.
6) Globally clocking state machines is the best way to avoid logic races. Another precaution is to use the master-slave structure, a slave feeding off the Q of each master, and clocking the slaves with an inverted clock or a delayed clock, and getting D gating for the master from only the slaves. This arrangement tolerates double clock pulses and reflected clocks. The white paper above seems to indicate that inverted global clocking for the slaves can be done in ATF15xx, and it may be just !a_slave.ck = glob_clk1; a_slave.d = whatever gating you need; in WinCUPL.
7) The simplest choice of flip flop is D. You can make a T by feeding back -Q to D, for rippled binary counters.
8) The general idea of PLD is "sum of products," wide AND gates feeding into three- to eight-wide OR. (AND-ORing) In a 16-pin PLD, the AND gates are normally 14-wide plus another 14 for the inverts. In Atmel ATF1504, the AND width is about 40 plus another 40 for inverts, it seems, and the OR are five-wide with about 2ns cascade adder to borrow more OR width from the next-up macrocell.
AND-ORing is what you naturally get from Karnaugh maps and truth tables, so AND-ORing is good. In a four-bit state machine, your typical D input might be, in terms of CUPL, B.d = A & !B & D # !A & !D . In the 1960s, before PLDs, a four-bit state machine would consume twenty TTL 14-pin packages, so PLDs are a great thing.
9) Reading Atmel CPLD literature is hard. a) There are plenty of options for different IC families that don't apply to your choice of IC, and that can get confusing. b) It is ambiguous what lines of code go with what software (CUPL, Verilog, etc.) c) There are so many abbreviations. PT is product term, MC is macrocell, LB is logic block, Gclk is global clock, CAS is cascaded OR, FF is flip flop, FB is feedback or foldback, .PLA is the compiled output file of CUPL which is needed by ProChip (a programmable logic array file), .PLD is the input file to the CUPL compiler (a programmable logic device file).
10) Learning simple gating can take five hours of instruction. Getting on board DeMorgan takes several hours. Karnaugh maps and truth tables is five hours, including practice to drive it home. State machine design for Moore is ten hours. There are many complexities of state machines, including races and how to handle more than five inputs. All these topics are two semesters in undergrad electrical engineering.
11) My preference for Karnaugh maps for state machines is to do the Karnaugh map just for the bits of the machine, which would be a 4x4 matrix for ABCD bits, up to 16 states. Handle the next-state logic by entering your external inputs into the map, instead of entering just zeros and ones. Example follows.
next B (B.d) = follow115kHz a !c !d + !a b d + b c d + a b c + trigger !hiFreq !a !b !c d + termCount !a !b c d + !termCount !a b c !d + !a !b c !d
CUPL has the ability to do state machines with a higher-level language, but I didn't find how to specify different clocks when you have two state machines in one CPLD, so I have just been doing my own state-machine equations and being really careful to find errors.
12) WinCUPL has great capabilities if you can get your mind around it all. Compilation errors are hard to find. You must have examples to start learning CUPL, and Atmel does have lots of examples, though not all for CPLD. CUPL has some bugs, and there is a minimal staff that maintains it. ProChip has plenty of quirks. "Try" to keep signals on the same pins has not worked well for me, and "keep" usually refuses to fit. My current approach to the software is to build up a complex CPLD in CUPL from a surest-to-work core (maybe preassign some pins into certain logic blocks for the high-frequency signals), cycle through ProChip to find any show stoppers, and go back and add function in CUPL, assigning pin numbers that ProChip has already fit.
13) Of four Windows XP PCs I have tried WinCUPL and ProChip on, some have run one or the other program but not both. I used USB memory to transfer the CUPL output, the .PLA file, over to the computer that ran ProChip. It was inconvenient. Only one computer of the four I have tried ran both CUPL and ProChip.
14) It is important that you set up a folder in Windows for your new CPLD. CUPL and ProChip generate about a dozen output files that will muck up other folders if you have revisions of your CPLD to work through.
15) In WinCUPL help is the CUPL Programmers Reference Guide. There is no global search, you have to click on one little chapter at a time. It is not written for newbies. I learned from the examples that Atmel gives on the installation from CD in the DK3 kit.
16) In the following two screens of ProChip, I found on July 20, 2015 that it matters which check boxes you check, if you are doing a revision of a design in WinCUPL & need to keep the same pins. If you check the wrong boxes, the fitter is likely to swirl around the pin assignments, necessitating a board redesign for your revision. (A given: Pin Fit Control "Keep" has not worked for me, the fitter chokes when you check Keep.)
What worked today is to look at the previous version's .fit report, near the top, where it says what it actually did as far as latch synthesis, cascade, etc. goes. As you move into ProChip for your revision, try to check the boxes to make it look like the previous fitter selections. I was able to get a minor revision done with no pin swirl, in a design 24Vsupplyv3 with 84-pin PLCC using 40 I/O pins, 21 flip flops (two state machines & some latches), and 8 cascades (including a lot of logic for "prioritized" 7-segment display). Twenty minutes before the successful ProChip run, when I had not taken care to do the right check boxes, the fitter put 30% of the pins at radically different positions, & I was afraid I would have to design & build a brand new board to fix a minor logic error.
Above is the Global Device tab of ProChip's fitter. There is a help screen but it is pretty obtuse. The settings shown are the ones I have been using. The choice for Not Gate Push Back is apparently to let the fitter push back an overall inversion (a "not gate") in terms of DeMorgan, which might help to simplify logic sometimes. Who knows if checking it would let Keep work more often?
Above is the Macrocell and I/O tab. Again, these are the choices I have been going with. When you have an output that needs to be open drain, you do that for just the pin(s) needing it, on the Pins tab. If you check Open Collector on this tab, every pin will be open drain, a disaster. If you have a design that uses global output enabling, you can check Global OE, but that may have a funny effect on pins that don't use output enabling, and you might need to turn it off for such pins on the Pins tab. Soft Buffer must be enabled on a pin by pin or node by node basis on the Pins tab, for signals that must not be simplified away, such as where you use delay through a macrocell to avoid a race. If you do this, look at the equations in the fitter file, *.fit, to see if the delay equation is really there.
Grayed-out options in fitter are for low-power Atmel CPLDs.
In July 2015, I found a $200 programmer (28 pin ZIF) in the Kanda.com web site. It is used by universities. It is good for EPROM & GAL, like 22V10 $3. 22V10 really looks like a CPLD, not just a PLD. I intend to order the kit & see if it is good for smaller projects. The DIP 22V10 needs a 24-pin socket & has to be pulled from the socket to reprogram. (It does not program by JTAG like Atmel ATF1504AS.)
A Sample, Large CUPL .PLD File
A Sample, Large CUPL .PLD File
The only space-saving CUPL feature I am using is list notation, like PIN [11,9,4] = [am,cm,dm] . There aren't enough examples of macros and state machines for me to figure out how they work, so a moderate design such as this looks long. You never end a signal name with a number unless you are doing a bit field on purpose. Therefore, I end signal names with alpha, such as 7_3728M or Atwelve instead of A12, except when I accidentally let andorutilin4 slip through, but it hasn't been keeping CUPL compile from working.
Even this moderate design can get you lost during revisions. Commenting helps. I also have logic diagrams and Karnaugh maps in pencil on paper, state diagram on CorelDRAW, system description in Open Office .ODT, and signal-flow block diagram on Linux Inkscape vector drawing. The 60MS/s digital storage oscilloscope application is pretty complex. Despite all this documentation, if I were to come back to it after a year and try to do a revision, I might be pretty much lost about why I did certain things certain ways.
Name LFSRn ; This section doesn't make too much difference except for two entries. 1) Name determines file
PartNo 2 ; names for all the output files. 2) Device should be virtual, ProChip New Design Wizard is where
Date 9/15/2012 ; you put in the actual device part number. Even so, any pin numbers you specify for input or output
Revision 01 ; will be worked into the .PLA file that goes into ProChip, so do this .PLD with a specific part
Designer John Engelbrecht ; in mind, including PLCC 84 pin or whatever.
Company Solder&Circuits ;
Assembly DSO ;
Location Grovetown ;
Device virtual ;
Copy and paste from Windows Notepad works, but never paste anything from Microsoft Word
Save often, 15% of commenting caused WinCUPL to crash
WinCUPL colorizing is buggy
/* Atmel ATF1504AS 84-pin PLCC*/ /* refer to state diagram ABCD State Machine to clock LFSR Addr Generator for SRAM July 27 2012
For DIY Dig Storage O'scope This CPLD 84pin J lead ATF1504AS is CPLD #2, */
/*has fast LFSR 12 bit plus A12 T flip flop for 13 address bits total. State machine ABCD and A12 clock at pin 83
rate, 60MHz, but ABCD stays put when A12 is low, so it looks like */ /* ABCD is clocking at 30MHz. */
/* LFSRb assigned only bm on 68, global clk 60M, result is scattered */
/* ripple clks and a,c,d masters in different logic blk from b. */ /* Attempt to assign some pins to give better order before proceeding*/
/* to LFSR. */
It is frustrating how ProChip ignores pin numbering when you TRY, but sometimes won't fit when you KEEP.
/* ver c/d asked for ABCD in logic block D but it was fitted into A. */ /* ver e is trying for input signals where CPLD Test Bed #1 has
switches, pins 15-18, 20-22, 24. That pretty much worked, and Test Bed #1 */ /* was used to verify logic of ABCD. By the way, both mas & slaves of ABCD */
/* are clked by 60MHz, so it isn't really 2-phase, but it is mas-sl & may be fine if confined to one logic block. */
/* Ver f attempts to add LFSR with real 2-ph clk & D logic including reset at 0000 & 1111 */
/* Try for LFSR mas in 1 logic blk & sla in another. */ /* Turns out that, allowing for cascading logic to get enough OR width */
/* for the XORs, 12-bit LFSR is as big as I can do in 1 logic blk. */
/* Hardware verif of f may be with no-socket board with only CPLD 2, 74F193, 120MHz sine osc, delay lines, 7.2728MHz osc, SRAM. */
/* during check of LFSRf, found I hadn't done shift for ABCD=0100, but also found that logic blows up
for the invert of the conditions when Q needs to be copied to D (the stay condition). */
/* All the LFSR D gating has enough setup time to be pre-combined as an output pin and utilized through
the global or regional bus, except Q when you "stay." So make that precombination in ver g. */
/* That was successful, and fitter has the flexibility to do eqns as not-ed on left side of = which can decrease product-term explosion. Fit of verF was successful! */
/*Used soft buffer on SHIFT, don't know if that was critical. Even XOR-ed Ds of LFSR needed only 5-way OR.*/
/* Nudge design toward final version. Get Atwelve out to pin, do OE for A12&Aslow that ORs them, add some delay chains to simulate nota12delayed delay line (for debug on Test Bed #2),*/
/* add 60MHz as an input in addition to global clock as it is needed for SRAM -WE (with delay-line drive & programmable inversion also), */
/*do GHJKclk with ANDing chain to suppress 2ns decode glitches, and do some utility AND OR INVERT that might be useful in case of logic errors*/
/* ver J, LFSRj.PLD 9-3-2012 add a syncing FF for 1001ghjk to reduce metastability because 1001ghjk decode is from the slow, GHJK st. mach.
and is pretty much unsynced to ABCD. */
/* ver K 9-14-12 forgot inverts on WEdellinenota,b. Also, do nota12delayed so no wires need be soldered, add more utility, just-in-case logic, and -A&C for gating -WE delay-line receiver. */
/* nota12delayed plan--not so easy since atwelve is output enabled for exterior ORing with aslow. Do a parallel FF, a12alt, */
/* with same inputs but no output pin & no OE. Use it merely to develop the delayed nota12delayed. */
/* a12alt(FF)--delay1 with invert, an output pin--delay2, an output pin--nota12delayed for LFSR slave clk */
/* *************** INPUT PINS *********************/ These commented markers for input, output, pinnode, equations are
just comments for readability. CUPL determines inputs and outputs based on being to the left of = or the right of =.
PIN 83 = 60M ; /* 60MHz if system can go that fast */
pin 15 = 60Malso; /* for developing SRAM -WE */
pin 12 = notWEdellinecontrol; /* programmable invert of diff signals going to -WE delay line */
PIN 10 = trig ; /* start a data capture of 8k samples */
PIN 22 = usefastclk ; /* if 0, use slowclk, 3.75MHz,.94MHz,or 29kHz coming in on a pin */
pin 8 = slowclk ; /* 3.75M, .94M, or 29kHz */
pin 2 = 7_3728M ; /* 7.3728 crystal osc, div down for 115.2kHz RS-232 rate */
pin 60 = 1001ghjk ; /* the serial st mach ghjk is 1001, byte has been sent */
pin 5 = utilinvertin;
pin 54 = andorutilin1; pin 37 = andorutilin2; pin 55 = andorutilin3; pin 73 = andorutilin4;
pin 17 = andorinvutilin1; pin 16 = andorinvutilin2; pin 39 = andorinvutilin3; pin 18 = andorinvutilin4;
/********* OUTPUT PINS *********************/
pin 6 = bm ; /* assign middle of ABCD to middle of logic block D */
PIN [11,9,4] = [am,cm,dm] ; /* state mach masters */
pin 61 = aslow; /*a version of a12 used for ABCD=0100 */
pin 80 = shift; /* combinatorial, must be combined to a pin or pinnode to keep !shift from blowing up in LFSR D eqns, would prefer it be in same logic blk as LFSR masters */
PIN 69 = ghjkclk_noglitch ; /*clock for serial comm state mach in CPLD 1 */
pin 81 = 3_69M; /*a cal signal for ADC */
pin [28,30,29,31] = [lfsr0m,lfsr1m,lfsr2m,lfsr3m];
pin 27 = lfsr4m; /* the leftmost LFSR master with XOR on D */
pin [34,33,35,58,57] = [lfsr5m,lfsr6m,lfsr7m,lfsr8m,lfsr9m];
pin [25,24] = [lfsr10m,lfsr11m]; /*both have XOR on D */
pin 56 = atwelve ; /* the only FF that actually goes at 60MHz clk, toggles to 30MHz at the Q */
pin 65 = WEdellinea; /* a & b are to one wire of delay line, paralleled */
pin 67 = WEdellineb;
pin 64 = WEdellinenota; /* nota & notb are to the other wire */
pin 63 = WEdellinenotb;
pin 44 = delay1out; /* to delay inverse of atwelve */
pin 21 = delay2out; /* more delay of A12 */
pin 36 = utilinvertout; pin 45 = andorutilout; pin 68 = andorinvutilout;
pin = WEgatesram; A new design may have blanks for all pin numbers. ProChip will assign global clock to what it thinks are your clocks. This example has most pins specified because my PCB is already laid out and I don't want ProChip to stir all the pins around when I have a revision. I looked at the .fit report from ProChip and copied pin numbers back into this revised .PLD .
/* *************** PINNODES *********************/ Pinnodes are macrocell outputs that are not needed as I/O pins. CPLD feeds them back into the global or regional bus and Atmel Logic Doubling lets ProChip use some of the leftover macrocell resources for other functions.
pinnode = a12alt;
pinnode = [as,bs,cs,ds] ; /* the slaves of am... */
pinnode = [1_84M,922k,461k,230k,115k ];
pinnode = termct ; /* LFSR is about to wrap to 10000... */
pinnode = [lfsr0s,lfsr1s,lfsr2s,lfsr3s,lfsr4s,lfsr5s, lfsr6s,lfsr7s,lfsr8s,lfsr9s,lfsr10s,lfsr11s];/*slaves*/
pinnode = ghjkclk_noglitchhelper;
pinnode = 1001ghjksync;
pinnode = WEgatehelper;
Every signal must have been listed above before being used in an equation, similar to typing in C language. Exception: if you have an intermediate (shorthand) term such as shiftslow = !usefastclk & atwelve & !am&!bm&cm&!dm ; , shiftslow must not be above equations.
/********** Equations *************/
WEgatehelper = !am&cm;
WEgatesram = WEgatehelper & !am&cm; /* deglitched, goes out to analog 60MHz clk delay-line receiver to gate it on during data recording */
1001ghjksync.d = 1001ghjk;1001ghjksync.ck = 60M;
delay1out = !a12alt;
delay2out = delay1out;
nota12delayed = delay2out; /* the clk for LFSR slave FFs, use soft buffer in ProChip5 so these aren't simplified, which would eliminate the delay. */
utilinvertout = !utilinvertin;
andorutilout = andorutilin1&andorutilin2 # andorutilin3& andorutilin4; Some just-in-case logic to use up NC pins
!andorinvutilout = andorinvutilin1&andorinvutilin2 # andorinvutilin3& andorinvutilin4;
Above, note the ! on the left of =. CUPL is fine with this but may choke if you have xxxx = !( big expression );
WEdellinea = notWEdellinecontrol & !60Malso # !notWEdellinecontrol & 60Malso; /* proper polarity of -WE to SRAM may require both this inversion control and changing receiver's bases on the two wires */
WEdellineb = notWEdellinecontrol & !60Malso # !notWEdellinecontrol & 60Malso; ATF1504AS has a lot of drive (PCI bus compatible if you parallel some pins) so I am driving a 100-ohm twisted-pair delay line from the pins.
WEdellinenota = notWEdellinecontrol & 60Malso # !notWEdellinecontrol & !60Malso;
WEdellinenotb = notWEdellinecontrol & 60Malso # !notWEdellinecontrol & !60Malso;
am.d = (!atwelve & am) # atwelve & (!as&bs&!cs&!ds # as&!cs&ds # as&bs&cs # termct&bs&cs&ds); State machine starts
bm1st = trig&usefastclk&!as&!bs&!cs&ds # bs&!ds ;
bm2nd = !as&cs&!ds # as&bs&cs # !termct&as&bs # (termct # usefastclk)&bs&cs;
bm.d = (!atwelve & bm) # atwelve & (bm1st # bm2nd ); At 60MHz clock, when a12 is low, I feed the master's own Q, bm, around to the D input. Otherwise, the D logic uses the slave Qs, buried in bm2nd and bm1st, to avoid races. Feeding back bm, Bmaster, may be key to stability, whereas using the slave, bs, might be too much delay. But there is no guarantee that even this will be stable.
cm.d = (!atwelve & cm) # atwelve & (trig&!as&!bs&ds # !as&cs # !115k&bs&cs # bs&cs&ds # !termct&!115k&as&bs&ds);
dm1st = trig&!as&!bs&!cs # !as&bs&!cs&!ds # !as&bs&cs&ds # !(!termct & !115k)&as&bs&!cs&ds;
dm2nd = slowclk&!as&cs&ds # 115k&bs&cs&ds # slowclk&!as&bs&!ds;
dm.d = (!atwelve & dm) # atwelve & (dm1st # dm2nd );
am.ck = 60M; bm.ck = 60M; cm.ck = 60M; dm.ck = 60M;
as.ck = 60M; bs.ck = 60M; cs.ck = 60M; ds.ck = 60M;
as.d = (atwelve & as) # (!atwelve & am); bs.d = (atwelve & bs) # (!atwelve & bm); cs.d = (atwelve & cs) # (!atwelve & cm);
ds.d = (atwelve & ds) # (!atwelve & dm); These are the slaves, to avoid races
atwelve.d = !atwelve ; /*& !(!am&!bm&!cm&dm); reset at ABCD=0001 but that made many .D inputs hang, so try without A12 reset, I think it will be fine */
atwelve.ck = 60M; atwelve.oe = !am&cm # !am&dm;
a12alt.d = !atwelve; /* must be this way so the two T FFs are in phase */ Without this comment, I wouldn't remember after a year why I had done such a strange thing
a12alt.ck = 60M;
aslow.d = aslow & (cm&!dm # !cm&dm # !bm # !am) # !aslow&am&bm&!cm&!dm; /* inverts at AB !C !D, zero at ABCD */
aslow.ck = 60M; aslow.oe = am&bm # !cm&!dm; /* notes Aug 30 2012 */
ghjkclk = am&bm&!cm&!dm;/*follows the lead of 115k, which is worked into the ABCD state machine. Has 2ns-wide slivers, only 33ns wide, goes to CPLD #1 */
ghjkclk_noglitchhelper = ghjkclk;
ghjkclk_noglitch=ghjkclk & ghjkclk_noglitchhelper; /* use soft buffer in Pro-Chip for both of these to keep them from being simplified */
3_69M.ck = 7_3728M; 3_69M.d = !3_69M; /* ripple-clock down to 115.2kHz */
1_84M.ck = 3_69M; 1_84M.d = !1_84M; 922k.ck = 1_84M; 922k.d = !922k; 461k.ck = 922k; 461k.d = !461k; 230k.ck = 461k; 230k.d = !230k; 115k.ck = 230k;
115k.d = !115k; /* is used by ABCD state mach */
termct = !lfsr0m & !lfsr1m & !lfsr2m & lfsr3m & !lfsr4m & !lfsr5m & !lfsr6m & !lfsr7m & !lfsr8m & lfsr9m & lfsr10m & lfsr11m ;
lfsrreset = !am&!bm&!cm&!dm # am&bm&cm&dm; /*resets to 100000000000 */
shiftsixty = usefastclk & atwelve & !am&bm&cm&dm ;/* this & next line are in the recording loop */
shiftslow = !usefastclk & atwelve & !am&!bm&cm&!dm ;
shiftserial = aslow & atwelve & 1001ghjksync & am & bm & !cm & !dm; /* in the playback loop */
shift = shiftsixty # shiftslow # shiftserial;
Linear feedback shift register is a whole topic unto itself. The fastest RAM address generation. Search for New Wave Instruments maximal length linear feedback shift register.
lfsr0m.d = lfsrreset # lfsr11s&shift # lfsr0m&!shift;/*shift rightmost slave bit in or keep master's present Q*/
lfsr1m.d = !lfsrreset & ( lfsr0s&shift # lfsr1m&!shift ); lfsr2m.d = !lfsrreset & ( lfsr1s&shift # lfsr2m&!shift );
lfsr3m.d = !lfsrreset & ( lfsr2s&shift # lfsr3m&!shift );
lfsr4m.d = !lfsrreset & ( (lfsr3s $ lfsr11s) &shift # lfsr4m&!shift );
/*above is the first XORed bit, using operator $ */
lfsr5m.d = !lfsrreset & ( lfsr4s&shift # lfsr5m&!shift ); lfsr6m.d = !lfsrreset & ( lfsr5s&shift # lfsr6m&!shift );
lfsr7m.d = !lfsrreset & ( lfsr6s&shift # lfsr7m&!shift ); lfsr8m.d = !lfsrreset & ( lfsr7s&shift # lfsr8m&!shift );
lfsr9m.d = !lfsrreset & ( lfsr8s&shift # lfsr9m&!shift );
lfsr10m.d = !lfsrreset & ( (lfsr9s $ lfsr11s) &shift # lfsr10m&!shift );
lfsr11m.d = !lfsrreset & ( (lfsr10s $ lfsr11s) &shift # lfsr11m&!shift );
lfsr0s.d = lfsr0m; /*lfsr slaves all have a delayed clk on globalclk2 ?, abt. 20ns delay */
lfsr1s.d = lfsr1m; lfsr2s.d = lfsr2m; lfsr3s.d = lfsr3m; lfsr4s.d = lfsr4m;
lfsr5s.d = lfsr5m; lfsr6s.d = lfsr6m; lfsr7s.d = lfsr7m; lfsr8s.d = lfsr8m;
lfsr9s.d = lfsr9m; lfsr10s.d = lfsr10m; lfsr11s.d = lfsr11m;
lfsr0m.ck = 60M; lfsr1m.ck = 60M; lfsr2m.ck = 60M; lfsr3m.ck = 60M; lfsr4m.ck = 60M; lfsr5m.ck = 60M; lfsr6m.ck = 60M; lfsr7m.ck = 60M;
lfsr8m.ck = 60M; lfsr9m.ck = 60M; lfsr10m.ck = 60M; lfsr11m.ck = 60M;
lfsr0s.ck = nota12delayed; lfsr1s.ck = nota12delayed; lfsr2s.ck = nota12delayed; lfsr3s.ck = nota12delayed;
lfsr4s.ck = nota12delayed; lfsr5s.ck = nota12delayed; lfsr6s.ck = nota12delayed; lfsr7s.ck = nota12delayed;
lfsr8s.ck = nota12delayed; lfsr9s.ck = nota12delayed; lfsr10s.ck = nota12delayed; lfsr11s.ck = nota12delayed;
End of example .PLD
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