Digital Circuits

Course Code : ECE111 (Received Teaching Excellence Award for this course in Monsoon-2019)

Credits : 4

Course website : https://www.usebackpack.com/iiitd/m2018/ece111

Overview

The aim of the course is to get the students through the process of Digital Circuit Design after introducing the students to signal representation, Boolean algebra, Logic Gates and Design with Logic Gates. Make them the aware of Combinational and Sequential Circuits and their Design approaches. The students will be exposed to pipelining concepts also.

Expected Outcome

After successfully completing the course, a student will have the capability to:

• 1. Translate a decision-making process into digital logic, Understand Number System and circuits realizing Arithmetic operations, Design simple digital circuits based on combinational logic.

  2. Distinguish between combinational and sequential logic, Design Asynchronous and Synchronous counters and Shift Registers.

1. Understand the concept of STD and STT and design Sequential Circuits and State Machines

2. Understand the pipelining concepts

Description

• Digital Processing of Information (2): Analog and Digital representations of information; Data vs signal; Information processing steps – logic and arithmetic.

• Digital Logic (4) – Binary variables; Basic logic operations – AND, OR, NOT; Basic gates; Essentials of Boolean algebra; De Morgan’s laws; Truth Table; Boolean functions; Transforming a logical problem statement into a Boolean expression.

• Number Systems and Arithmetic (4): Positional number systems – Binary, Decimal, Octal, Hexadecimal; Signed number representations; Arithmetic operations.

• Combinational Circuit Design (10) – Realisation of Boolean functions using gates; Karnaugh map; Minimisation of Boolean functions; Multiplexer-based realization of K-maps; Combinational circuit design using multiplexers and gates.

• Sequential Circuit Design (9) – Latches and Flip-flops; Ripple counters; Sequence generator using flip-flops; State Table and State Diagram; Synchronous counters; Shift Registers; Ring and MLS counters.

• Pipelining: Pipelining with Edge Triggered Flip Flop, Pulse Triggered Flip Flop and Latches. Introduce the concepts of Skew and Jitter (4 hrs)

Evaluation

• • Mid-sem-20%

  • End-sem-40%

  • Assignments-10%

  • Laboratory-15%

  • Quizes (Best N-1 out of N)-15%

Policies

Refer to the first lecture

Textbooks

• • Digital Design – M. Morris Mano & Michael D. Ciletti, Ed-5, Pearson (Prentice-Hall).

  • Fundamentals of Digital Logic with Verilog Design - S. Brown, Z. Vranesic, Ed-3, McGraw-Hill