Publications
Books
S. Saurabh, Introduction to VLSI Design Flow, Cambridge University Press, ISBN:9781009200790, April 2023
Sneh Saurabh and Mamidala Jagadesh Kumar, Fundamentals of Tunnel Field Effect Transistors, CRC Press (Taylor & Francis), ISBN 9781498767132. November 2016
Book Chapters
S. Saurabh, P. Jain, M. Agarwal, and O.S. Ram, Applications of Machine Learning in VLSI Design, In VLSI and Hardware Implementations Using Modern Machine Learning Methods, pp. 125-139, CRC Press, 2022.
S Saurabh, SK Semwal, S Garg, A Gupta, Emerging devices beyond CMOS: fundamentals, promises and challenges, VLSI and Post-CMOS Electronics: Design, Modelling and Simulation, IET, September 2019
Journals
A. Gupta and S. Saurabh, "Unsupervised Learning in a Ternary SNN Using STDP," IEEE Journal of the Electron Devices Society, Feb 2024 (Early access).
J. Kaur, S. Saurabh, and S. Sahay. "Bilayer Synthetic Antiferromagnetic Skyrmion-based Muller C-element," in IEEE Transactions on Electron Devices, vol. 71, pp. 516-523, Jan 2024 (Link to paper ).
A. Gupta and S. Saurabh, "On-chip Unsupervised Learning using STDP in a Spiking Neural Network", IEEE Transactions on Nanotechnology, vol. 22, pp. 365-376, July 2023 (Link to paper ).
Syed Asrar ul haq, Abdul Karim Gizzini, Shakti Shrey, Sumit J. Darak, Sneh Saurabh and Marwa Chafii, "Deep Neural Network Augmented Wireless Channel Estimation for Preamble-based OFDM PHY on Zynq System on Chip", IEEE Transactions on Very Large Scale Integration Systems, vol. 31, pp. 1026-1038, July 2023 (Link to paper)
A. Gupta and S. Saurabh, "An Energy-efficient Ge-based Leaky Integrate and Fire Neuron: Proposal and Analysis", IEEE Transactions on Nanotechnology, vol. 21, pp. 555-563, Sept. 2022 (Link to paper ).
J. Kaur, S. Saurabh, and S. Sahay. "Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference." IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, pp. 750-761, Sept. 2022 (Link to paper).
A. Gupta and S. Saurabh, "Novel attributes of a dual pocket tunnel field-effect transistor", Japanese Journal of Applied Physics, vol. 61, no. 03, Feb 2022 (Link to paper).
M. K. Ram, N. Tiwari, D.B. Abdi, and S. Saurabh , "Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis", IEEE Access, vol. 9, pp. 150366-150372, Nov. 2021 (Link to paper)
M. K. Ram, N. Tiwari, D.B. Abdi, and S. Saurabh , "Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study", IEEE Access, vol. 9, pp. 141321-141328, Oct. 2021 (Link to paper)
Abhinav Gupta and Sneh Saurabh, "Implementing a Ternary Inverter Using Dual-Pocket Tunnel Field-Effect Transistors", IEEE Transactions on Electron Devices, Sept 2021, (Link to paper)
Shelly Garg and Sneh Saurabh, "Implementation of Boolean Functions using Tunnel Field-Effect Transistors", IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, Dec. 2020, (Link to paper)
Shelly Garg and Sneh Saurabh, "Exploiting Within-Channel Tunneling in a Nanoscale Tunnel Field-Effect Transistor" IEEE Open Journal of Nanotechnology, vol. 1, pp. 100-108, Oct 2020, (Link to paper)
Shelly Garg and Sneh Saurabh, "Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors," IEEE Journal of the Electron Devices Society, vol. 8, pp. 1001-1009, Aug 2020, (Link to paper)
OVS Shashank Ram and Sneh Saurabh, "Modeling Multiple Input Switching in Timing Analysis using Machine Learning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2020, (Link to paper)
Shelly Garg and Sneh Saurabh, "Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis", IEEE Access, vol. 7, pp. 117591-117599, Sept 2019 (Link to paper)
Akhil James and Sneh Saurabh, "Dopingless 1T DRAM: Proposal, Design and Analysis", IEEE Access, vol. 7, pp. 88960-88969, June 2019 (Link to the paper)
Varshita Gupta, Shagun Kapur, Sneh Saurabh and Anuj Grover, "Resistive Random Access Memory: A Review of Device Challenges", IETE Technical Review, June 2019 (Link to paper)
Shelly Garg and Sneh Saurabh, "Improving the scalability of SOI-based Tunnel FETs using Ground Plane in Buried Oxide", in IEEE Journal of the Electron Devices Society, vol. 7, pp. 435-443, April 2019, (Link to paper)
Sneh Saurabh, Hitarth Shah and Shivendra Singh, "Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions" IETE Technical Review, October 2018, pp. 1-14, (Link to paper)
Saptak Banerjee, Shelly Garg and Sneh Saurabh, "Realizing logic functions using single Double-Gate Tunnel FETs: A simulation study", IEEE Electron Device Letters, Vol. 39, pp. 773-776, May 2018 (Link to paper)
Shelly Garg and S Saurabh, "Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis", Superlattices and Microstructures, Vol. 113, pp. 261-270, January 2018 (Link to paper)
Sneh Saurabh and M. Jagadesh Kumar, "Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor," IEEE Trans. on on Electron Devices, Vol.58, pp. 404-410, February 2011 (Link to paper)
Sneh Saurabh and M. Jagadesh Kumar, "Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability," IEEE Trans. on Device and Materials Reliability, Vol.10, pp. 390 - 395, September 2010 (Link to paper)
Sneh Saurabh and M. Jagadesh Kumar, "Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor (TFET): Theoretical Investigation and Analysis," Japanese Journal of Applied Physics, Vol.48, paper no. 064503, June 2009 (Link to paper)
Conferences/Workshops
Pooja Beniwal and Sneh Saurabh, "Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement", in 37th International Conference on VLSI Design (VLSID) 2024 , Jan (Link to the paper)
Pranav Jain, Gagandeep, and Sneh Saurabh, "FLIP: An Artificial Neural Network-based Post-routing Incremental Placer", in 37th International Conference on VLSI Design (VLSID) 2024 , Jan 2024 (Link to the paper)
Shivendra Singh, Ekta Tiwari, and Sneh Saurabh, "Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis," in 37th International Conference on VLSI Design (VLSID) 2024 , Jan 2024 (Link to the paper)
Dikshant Yadav, Priyanka Bhagat, Pooja Beniwal and Sneh Saurabh, "CoDriVer: A Tool for Coverage-driven Functional Verification of RISC-V Processors" presented at 27th International Symposium on VLSI Design and Test (VDAT 2023), BITS Pilani, Sept. 2023
Amina Haroon, Ram Krishna Ghosh, and Sneh Saurabh, "Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis", in 36th International Conference on VLSI Design (VLSID) 2023 , Oct. 2022 (Link to paper)
Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, and Sneh Saurabh, "A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking", in 30th VLSI-SoC, Patras, Greece, Oct. 2022 (Link to paper )
Amina Haroon and Sneh Saurabh, "Image Completion using a Sparse Probabilistic Spin Logic Network", in 35th International Conference on VLSI Design (VLSID) 2022 , Jan. 2022 (Link to paper)
Madhvi Agarwal and Sneh Saurabh, "An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network " in MLCAD 2021 (3rd ACM/IEEE Workshop on Machine Learning for CAD) , Sept 2021 (Link to the paper)
Akshay Balaji and Sneh Saurabh, "Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate–Source Underlap," VLSI-SOC 2021, Singapore, Aug 2021
S. Poria, S. Garg, and S. Saurabh, "Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate", in 24th International Symposium on VLSI Design and Test (VDAT 2020), July 2020 (Link to the paper)
Vaibhav Agarwal and Sneh Saurabh, "Application of Probabilistic Spin Logic (PSL) in detecting satisfiability of a Boolean function", 20th International Symposium on Quality Electronic Design (ISQED 2019), March 2019, Santa Clara, California, USA (Link to the paper)
Vaibhav Agarwal and Sneh Saurabh, "Realizing Boolean functions using Probabilistic Spin Logic (PSL)", 32nd International Conference on VLSI Design (VLSID) 2019, Jan 2019, Delhi, India, (Link to the paper)
Sneh Saurabh and Vishav Vikash, "Assessing the impact of temperature and supply voltage variations in near-threshold circuits using an analytical model", ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, May 2018, Chicago, Illinois, U.S.A. (Link to the paper)
Sneh Saurabh and Priyanka Mittal, "A Practical Methodology to Compress Technology Libraries using Recursive Polynomial Representation", 31st International Conference on VLSI Design (VLSID) 2018, Jan 2018, Pune, India (Link to the paper)
Sneh Saurabh and Naresh Kumar, "An efficient methodology for model extraction using waveform analysis", ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop), March 2016, Santa Rosa, California, U.S.A. (PDF)
Sneh Saurabh and M. Jagadesh Kumar, "Mitigating the Delayed Current Saturation in a Nanoscale Tunnel Field Effect Transistor (TFET), " Accepted at the TechConnect World Conference and Expo 2010, June 21-25, 2010 in Anaheim, California, U.S.A.
Sneh Saurabh and M. Jagadesh Kumar, "Tunnel Field Effect Transistor with Strained Silicon Thinfilm for improving Immunity against Process Induced Variations" Accepted in IEEE TENCON 2008
M. Jagadesh Kumar and Sneh Saurabh, "Tunnel Field Effect Transistor (TFET) with Strained Silicon Thinfilm Body for Enhanced Drain Current and Pragmatic Threshold Voltage," 2008 NSTI Nanotechnology Conference and Trade Show, June 1-5, 2008, Boston, Massachusetts, U.S.A. (PDF)
