VLSI Design Flow

Course Code                : ECE513 (Received Teaching Excellence Award for this course in Monsoon-2016, Monsoon-2017 and Monsoon-2018) 

Semesters: Monsoon-2016, Monsoon-2017, Monsoon-2018, Winter-2020, Winter-2021, Winter-2022, Winter-2023, Winter-2024

Credits                          : 4

Course website            : Here 

Overview

The objective of this course is to develop a basic understanding of the methods, tools and technologies that go into transforming an “idea” into an “integrated circuit”. This course is intended to give an overall perspective of the VLSI design flow, going through various stages of designing such as synthesis, floor-planning, placement, routing etc. and various steps of verification such as simulation, formal methods and timing/power analysis. In this course, ample opportunities will be provided to employ the-state-of-the-art CAD tools and gain a practical understanding of the VLSI design flow. A few representative algorithms that work inside the CAD tools will also be discussed. 

Description

Expected Outcome:

At the end of the course the student:

• • Clearly understands each design and verification step in the VLSI design flow, and its purpose/significance

  • Is able to evaluate various trade-offs that need to be made at various steps in the VLSI design flow

  • Is able to design and verify simple VLSI circuits using the state-of-the-art computer aided design (CAD) tools at different levels of abstractions.

  • Understands a few representative algorithms that are used in implementing CAD tools

Course Content (Week-wise schedule):

1. Introduction: Basic Concepts; Design Styles; Designing vs. Fabrication; Processes involved in taking an "Idea" to RTL: Software/Hardware Partitioning, Behavioral Synthesis

2. Overview of "RTL to GDS" Design, Verification and Test Flow; Processes after GDS Tapeout to Final Chip;

3. Design capture: HDL (Verilog), RTL Simulation and Synthesis; 

4. Introduction to Formal Methods: Equivalence Checking, BDD, SAT;

5. Library and Constraints; Static Timing Analysis; Power Analysis;

6. Logic Synthesis: Optimization, Technology Mapping;

7. Design for Test (DFT): Fault Models, Scan Insertion

8. ATPG, BIST

9. Basic Concepts for Physical Design

10. Partitioning, Floorplanning, Power Planning; 

11. Placement: Techniques and Optimization; Clock Tree Synthesis: Distribution, Skew Optimization;

12. Routing: Global and Detailed; Physical Verification: Extraction, LVS, ERC, DRC; 

13. ECO, Sign-off, Post-silicon Validation

Evaluation

• • Assignment-15%

  • Project-20%

  • Mid-sem-25%

  • End-sem-40%

Pre-requisites (Mandatory)

• Digital Circuits

• Basics of CMOS Inverter

Textbooks

• S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023.