About Me

I was born and brought up in Bhagalpur, a historical city on the southern banks of the river Ganges, famous for its silk industry, ancient Vikramshila University and being home to the Gangetic Dolphins (the National Aquatic Animal of India). I did my schooling at St. Joseph's School and TNB College, Bhagalpur. During my schooling, I was fortunate to have great teachers such as Fr. Varghese Panangatt who considered inculcating human values among students as the prime motive of education.

I completed my B. Tech. from IIT Kharagpur in 2000 and PhD from IIT Delhi in 2012, both from the Department of Electrical Engineering. During my PhD, I was initiated to work on electronic devices by my adviser Dr. M. Jagadesh Kumar, a renowned academician and a distinguished researcher. The topic of my research was "Nano-scale Tunnel Field Effect Transistors for CMOS applications". I have worked extensively on Tunnel Transistors or “Green Transistors” and other nanoscale futuristic devices.

Currently, I am a Professor at IIIT Delhi in the Department of Electronics and Communication Engineering. Before joining IIIT Delhi in June 2016, I worked in the semiconductor industry for around sixteen years. My primary motivation for moving into academics after a long career in the industry is my love for learning/teaching and my enthusiasm for carrying out independent research in the areas of interest to me. In the past, I have taken up positions of technical leadership at:

• Cadence Design Systems [2012-2016]

• Synopsys India (including Magma DA and Atrenta India) [2001-2012]

• Delsoft India [2000-2001]

I have expertise in the areas of Static Timing Analysis, Design Implementation, Logic and Physical Synthesis, Timing Optimization and Formal Verification. My work in the industry has centred on tackling challenges that arise due to the scaling of transistors and the associated fall-out on the complexity of IC design and verification.

My current research interests are in the areas of:

• Nanoelectronics

• CAD for VLSI (especially application of Machine Learning)

• Energy-Efficient Systems

I have published several papers in reputed journals, hold 3 US patents and I am the author of the book Introduction to VLSI Design Flow and  Fundamentals of Tunnel Field-Effect Transistors. Currently, I am an Editor of IETE Technical Review and an Associate Editor of IEEE Access. I am a Senior Member, IEEE.

Besides academics, I enjoy long-distance running (marathons).