Team 

PhD

Current Students:

• Varun: PhD23111: Exploratory Materials to Systems (Joint supervisor Dr. R.K. Ghosh, IIIT Delhi)

• Misbah Fatima: PhD23102: Exploratory Nanoelectronic Devices

• Pooja Beniwal: PhD20111: Machine Learning for VLSI Design 

• Jasmine Kaur: PhD20102:  Nanoelectronic Devices and Memories (Joint supervisor Dr. Shubham Sahay, IIT Kanpur)

• Amina Haroon: PhD18105: Probabilistic Spin Logic (Link to her website )

Past Students:

• Abhinav Gupta: PhD18106: Implementation of Neuromorphic Computing Framework using Tunneling-based Devices

• Shelly Garg: PhD16109: Nanoscale Tunnel Field-Effect Transistors for Digital Circuit Applications: Design and Analysis

M.Tech. Thesis

        Current Students:

• • • Mohd Abu Ubaida: MT23216: Accounting Process-induced Variations more realistically

        Past Students:

• • • Prashasti Pandey: MT22188: Accounting for the Correlation between Low-threshold and High-threshold Transistors using Analytical Techniques

    • Gagandeep: MT20320: An artificial neural network based incremental placer for wire length reduction (1 paper in VLSID 2024). Currently at Synopsys NOIDA

    • Rajat Kumar: MT20321: "A Practical Methodology to Waive Marginal Timing Violations using Machine Learning". Currently at Synopsys NOIDA

    • Madhvi Agarwal: MT19183: An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network (1 paper in MLCAD 2021). Currently at Qualcomm India Pvt. Ltd.

    • Pranav Jain: MT19207: Applying Machine Learning methods for Incremental Placement of Digital Circuits (1 paper in VLSID 2024), Currently at Qualcomm India Pvt. Ltd.

    • Shubham Baunthiyal: MT19195: A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence (1 Paper in 30th VLSI-SoC), Currently at Synopsys, NOIDA

    • Akshay: MT18193: Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate Position Optimization (1 paper in VLSI-SoC 2021). Currently at Qualcomm India Pvt. Ltd., NOIDA

    • Jasmine Kaur: MT18202: Modelling and Simulation of Programmable Metallization Cell (PMCs) and Muller C-element. Currently pursuing PhD at IIIT, Delhi

    • Ishan Bhatia: MT17092: Investigation of Timing of Logic Gates realized using Probabilistic Spin Logic (PSL). Currently at Synopsys, NOIDA

• Nimish Agarwal: MT17104: Improving the Retention Time of a Dopingless 1T DRAM using Gate Engineering. Currently at Qualcomm India Pvt. Ltd., NOIDA

• Subhadip Poria: MT17124: Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate (1 paper in VDAT 2020). Currently pursuing PhD at IIT, Guwahati

• OVS Shashank Ram: MT17105: Modeling Multiple Input Switching in Timing Analysis using Machine Learning (1 paper in IEEE TCAD). Currently at Qualcomm India Pvt. Ltd., Bangalore

• Saptak Banerjee: MT16110: Logic gates using TFETs [Winner of The Best Thesis Award] (1 paper published in Electron Device Letters). Currently at Qualcomm India Pvt. Ltd., Bangalore

• Vaibhav Agarwal: MT16119: Probabilistic Spin Logic (PSL) (1 paper in ISQED-2019 and 1 paper in VLSID-2019). Currently at Cadence Design Systems, Bangalore

• Akhil James: MT16084: DRAMs using futuristic devices (1 paper published in IEEE Access) Currently at Qualcomm India Pvt. Ltd.

• Vishav Vikash: MT15117: Near Threshold Computing (1 paper published in GLSVLSI-2018). Currently at Qualcomm India Pvt. Ltd., Bangalore

Capstone Project and Independent Study/Project (Past Students)

• • • Shivendra Singh: MT21209: Novel DRAM Devices (1 Paper in VLSID 2024)

    • Ekta Tiwari: MT21152: Novel DRAM Devices (1 Paper in VLSID 2024)

    • Dikshant Yadav: MT21168, Functional Verification of RISC V Processors (1 Paper in VDAT23). 

    • Priyanka Bhagat: MT21158, Functional Verification of RISC V Processors (1 Paper in VDAT23). 

    • Shakti Shrey: MT20323, RTL to GDS Flow (1 paper in IEEE TVLSI).

    • Raiyyan Malik: MT20151, Combinational Equivalence Checking (1 Paper in 30th VLSI-SoC)

    • Puneet Kumar: MT19189: Combinational Equivalence Checking (1 Paper in 30th VLSI-SoC)

    • Srinath J: MT19197, Combinational Equivalence Checking (1 Paper in 30th VLSI-SoC)

    • Hitarth Shah: MT17120: Timing Closure Problem (1 paper accepted in IETE Technical Review).

    • Priyanka Mittal: MT16103: Library Compression (1 paper published in VLSID-2018).

B.Tech. Project (Past Students)

• Ankit  Girdhar: 2014136: Pitfalls of Timing Closure using Extracted Timing Model

• Varshita Gupta: 2015187: RRAM (1 paper published in IETE Technical Review)

• Shagun Kapur: 2015175: RRAM (1 paper published in IETE Technical Review)

Note to prospective students:

If you want to work with me, you may seek appointment by sending an email to: sneh@iiitd.ac.in. Based on your skill-set, research interests and academic background, I will inform you of an appropriate time to meet. I expect that you attach your latest CV and clearly state your research interests in your email.

Currently, I am looking for PhD candidates with interest in nano-electronics. Ideally, the candidate should have a good background of solid-state devices (p-n junctions, MOSFETs etc.), though this is not a pre-requisite since I believe that the understanding of solid-state devices can be quickly developed during PhD if a student has a keen interest in it. I expect that the candidate should possess good analytical skills, be eager to learn physics/modeling of devices and be inclined towards academics, in general.

Currently, I am also looking for industry sponsored PhD candidates to work in the area of application of Machine Learning in EDA. The details of the sponsored PhD program at IIITD can be found at: https://iiitd.ac.in/admission/phd/sponsored.